Datasheet

SN74SSTL32877
26-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
DESIGN GOAL
SCES241A – APRIL 1999 – REVISED MAY 1999
6–31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.5 V ± 0.2 V
V
CC
/2
V
CC
/2
V
REF
†
V
REF
†
V
REF
†
V
REF
†
V
REF
†
V
REF
†
V
OH
V
OL
t
h
t
su
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
V
IL
§
V
OL
+ 0.15 V
V
OH
– 0.15 V
0 V
V
IH
‡
V
IL
§
V
IL
§
t
w
V
IH
‡
V
IH
‡
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
†
V
REF
= V
DDQ
/2
‡
V
IH
= V
REF
+ 350 mV (ac voltage levels) for SSTL inputs. V
IH
= V
CC
for LVTTL inputs.
§
V
IL
= V
REF
– 350 mV (ac voltage levels) for SSTL inputs. V
IL
= GND for LVTTL inputs.
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z
O
= 50 Ω, t
r
≤ 2 ns, t
f
≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. V
TT
= V
REF
= V
DDQ
/2
F. t
PLZ
and t
PHZ
are the same as t
dis
.
G. t
PZL
and t
PZH
are the same as t
en
.
H. t
PLH
and t
PHL
are the same as t
pd
.
V
IL
§
V
IH
‡
V
REF
†
t
PHL
V
REF
†
V
REF
†
V
IH
‡
V
IL
§
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
V
REF
†
V
REF
†
t
PLH
V
CC
LOAD CIRCUIT
25 Ω = SSTL_2 Class II
C
L
= 10 pF or 30 pF
(see Note A)
Test
Point
V
TT
25 Ω
50 Ω = SSTL_2 Class I
Figure 1. Load Circuit and Voltage Waveforms
PRODUCT PREVIEW