Datasheet

SN74SSTL32877
26-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
DESIGN GOAL
SCES241A APRIL 1999 REVISED MAY 1999
627
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D Member of the Texas Instruments
WidebusFamily
D Supports SSTL_2 Signal Data Inputs and
Outputs
D Supports LVTTL Switching Levels on the
RESET
Pin
D Flow-Through Architecture Optimizes PCB
Layout
D Differential CLK Signal
D Meets SSTL_2 Class I and Class II
Specifications
D Packaged in Plastic Fine-Pitch
Ball-Grid-Array Package
description
This 26-bit registered buffer is designed for 2.3-V to 2.7-V V
CC
operation and SSTL_2 input and output levels.
Data flow from A to Y is controlled by differential clock (CLK, CLK
) inputs, the SSTL_2 output-enable (OE) input,
and the LVTTL reset (RESET
) input. Data are triggered on the positive edge of the positive clock (CLK). The
negative clock (CLK
) must be used to maintain noise margins. When RESET is low, all registers are reset, and
all outputs are low.
To ensure defined outputs from the register before a stable clock has been supplied, RESET
must be held in
the low state during power up.
The SN74SSTL32877 is characterized for operation from 0°C to 70°C.
terminal assignments
123456
A A1 V
CC
GND V
DDQ
Y1 Y2
B A3 A2 V
REF
GND Y3 Y4
C A5 A4 NC GND Y5 Y6
D A7 A6 GND V
DDQ
Y7 Y8
E A9 A8 V
CC
GND Y9 V
DDQ
F A11 A10 GND V
DDQ
Y10 GND
G A13 A12 V
CC
V
DDQ
Y12 Y11
H A15 A14 GND GND GND Y13
J CLK NC GND GND GND Y14
K CLK RESET V
CC
V
DDQ
Y15 Y16
L A16 A17 GND V
DDQ
Y17 GND
M A18 A19 V
CC
GND Y18 V
DDQ
N A20 A21 GND V
DDQ
Y20 Y19
P A22 A23 NC GND Y22 Y21
R A24 A25 OE GND Y24 Y23
T A26 V
CC
GND V
DDQ
Y26 Y25
PRODUCT PREVIEW
DESIGN GOAL
Copyright 1999, Texas Instruments Incorporated
Widebus is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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