Datasheet

SN74SSTL32867
26-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS
DESIGN GOAL
SCES240A – APRIL 1999 – REVISED MAY 1999
6–25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.5 V ± 0.2 V
t
h
t
su
LOAD CIRCUIT
V
REF
†
V
IH
‡
V
IL
§
V
REF
†
V
REF
†
V
IH
‡
V
IL
§
V
IH
‡
V
IL
§
V
REF
†
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
V
REF
†
V
REF
†
V
IH
‡
V
IL
§
V
CC
/2 V
CC
/2
V
OH
V
OL
Input
Output
C
L
= 10 pF or 30 pF
(see Note A)
Test
Point
V
REF
†
†
V
REF
= V
DDQ
/2
‡
V
IH
= V
REF
+350mV (ac voltage levels) for SSTL inputs. V
IH
= V
CC
for LVTTL inputs.
§
V
IL
= V
REF
–350mV (ac voltage levels) for SSTL inputs. V
IL
= GND for LVTTL inputs.
NOTES: A. C
L
includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z
O
= 50 Ω, t
r
≤ 1.25 ns/V,
t
f
≤ 1.25 ns/V.
C. The outputs are measured one at a time with one transition per measurement.
D. t
PLH
and t
PHL
are the same as t
pd
.
Timing
Input
Data
Input
From Output
Under Test
Figure 1. Load Circuit and Voltage Waveforms
PRODUCT PREVIEW