Datasheet

SN74SSTL32867
26-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS
DESIGN GOAL
SCES240A – APRIL 1999 – REVISED MAY 1999
6–24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V
CC
= 2.5 V ± 0.2 V
MIN TYP MAX
UNIT
f
clock
Clock frequency 200 MHz
t
w
Pulse duration, CLK, CLK high or low 1.6 0.8 ns
Data before CLK↑, CLK↓ 1.1 0.5
t
su
Setup time
RESET high before CLK↑, CLK↓ 1.1 0.5
ns
t
h
Hold time, data after CLK↑, CLK↓ 0.5 0 ns
switching characteristics over recommended operating free-air temperature range,
V
REF
= V
DDQ
/2 and C
L
= 10 pF (unless otherwise noted) (see Figure 1)
FROM TO
V
CC
= 2.5 V ± 0.2 V
PARAMETER
(INPUT) (OUTPUT)
MIN TYP MAX
UNIT
f
max
200 MHz
t
pd
CLK and CLK Y 1.9 2.8 ns
t
PHL
RESET
Y 2.2 3.2 ns
switching characteristics over recommended operating free-air temperature range,
V
REF
= V
DDQ
/2 and C
L
= 30 pF (unless otherwise noted) (see Figure 1)
FROM TO
V
CC
= 2.5 V ± 0.2 V
PARAMETER
(INPUT) (OUTPUT)
MIN TYP MAX
UNIT
f
max
200 MHz
t
pd
CLK and CLK Y 2.6 3.8 ns
t
PHL
RESET
Y 2.9 4.4 ns
PRODUCT PREVIEW