Datasheet

SN74SSTL16857
14-BIT SSTL_2 REGISTERED BUFFER
SCAS625 – FEBRUARY 1999
6–15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus Family
D Supports SSTL_2 Signal Data Inputs and
Outputs
D Supports LVTTL Switching Levels on the
RESET
Pin
D Differential CLK Signal
D Flow-Through Architecture Optimizes PCB
Layout
D Meets SSTL_2 Class I and Class II
Specifications
D Packaged in Plastic Thin Shrink
Small-Outline Package
description
This 14-bit registered buffer is designed for 2.3-V
to 3.6-V V
CC
operation and SSTL_2 input and
output levels.
Data flow from D to Q is controlled by differential
clock pins (CLK, CLK
) and the RESET. Data are
triggered on the positive edge of the positive clock
(CLK). The negative clock (CLK
) must be used to
maintain noise margins. When RESET
is low, all
registers are reset, and all outputs are low.
To ensure defined outputs from the register before
a stable clock has been supplied, RESET must be
held in the low state during power up.
The SN74SSTL16857 is characterized for
operation from 0°C to 70°C.
PRODUCT PREVIEW
Copyright  1999, Texas Instruments Incorporated
Widebus is a trademark of Texas Instruments Incorporated.
DGG PACKAGE
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Q1
Q2
GND
V
DDQ
Q3
Q4
Q5
GND
V
DDQ
Q6
Q7
V
DDQ
GND
Q8
Q9
V
DDQ
GND
Q10
Q11
Q12
V
DDQ
GND
Q13
Q14
D1
D2
GND
V
CC
D3
D4
D5
D6
D7
CLK
CLK
V
CC
GND
V
REF
RESET
D8
D9
D10
D11
D12
V
CC
GND
D13
D14
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.