Datasheet

SN74SSTL16837A
20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998
6–7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
h
t
su
LOAD CIRCUIT
Data Input
Timing Input
1.9 V
1.1 V
1.9 V
1.1 V
1.9 V
1.1 V
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
Output
Waveform 1
(see Note B)
Output
Waveform 2
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
V
TT
1.1 V
V
TT
1.9 V
Output
Control
t
PLH
t
PHL
1.9 V
1.1 V
V
OH
V
OL
Input
Output
25 Ω = SSTL_3 Class II
50 Ω = SSTL_3 Class I
C
L
= 10 pF or 30 pF
(see Note A)
Test
Point
V
TT
25 Ω
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z
O
= 50 Ω, t
r
≤ 1 ns, t
f
≤ 1 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. V
TT
= V
REF
= V
CC
× 0.45
F. t
PLZ
and t
PHZ
are the same as t
dis
.
G. t
PZL
and t
PZH
are the same as t
en
.
H. t
PHL
and t
PLH
are the same as t
pd
.
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.1 V
1.1 V
1.9 V 1.9 V
Figure 1. Load Circuit and Voltage Waveforms