Datasheet
SN74SSTL16837A
20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998
6–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus Family
D Supports SSTL_3 Signal Inputs and
Outputs
D Flow-Through Architecture Optimizes PCB
Layout
D Meets SSTL_3 Class I and Class II
Specifications
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D Packaged in Plastic Thin Shrink
Small-Outline Package
description
This 20-bit universal bus driver is designed for 3-V
to 3.6-V V
CC
operation and SSTL_3 or LVTTL I/O
levels.
Data flow from A to Y is controlled by the
output-enable (OE
) input. The device operates in
the transparent mode when latch enable (LE) is
high. The A data is latched if LE is low and clock
(CLK) is held at a high or low logic level. If LE is
low, the A data is stored in the latch/flip-flop on the
low-to-high transition of CLK. When OE
is high,
the outputs are in the high-impedance state.
To ensure the high-impedance state during power
up or power down, OE
should be tied to V
CC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
The SN74SSTL16837A is characterized for
operation from 0°C to 70°C.
Copyright 1998, Texas Instruments Incorporated
Widebus is a trademark of Texas Instruments Incorporated.
DGG PACKAGE
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Y1
Y2
GND
Y3
Y4
V
DDQ
Y5
Y6
GND
Y7
Y8
V
DDQ
Y9
Y10
GND
OE
V
REF
GND
Y11
Y12
V
DDQ
Y13
Y14
GND
Y15
Y16
V
DDQ
Y17
Y18
GND
Y19
Y20
A1
A2
GND
A3
A4
V
CC
A5
A6
GND
A7
A8
V
CC
A9
A10
GND
CLK
LE
GND
A11
A12
V
CC
A13
A14
GND
A15
A16
V
CC
A17
A18
GND
A19
A20
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.