Datasheet
SN74ALVCHR162409
9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES056F – SEPTEMBER 1995 – REVISED FEBRUARY 1999
4–95
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus+ Family
D EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
D B-Port Outputs Have Equivalent 26-Ω
Series Resistors, So No External Resistors
Are Required
D UBE (Universal Bus Exchanger) Allows
Synchronous Data Exchange
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
NOTE: For order entry:
The DGG package is abbreviated to G.
description
This 9-bit, 4-port universal bus exchanger is
designed for 1.65-V to 3.6-V V
CC
operation.
The SN74ALVCHR162409 allows synchronous
data exchange between four different buses. Data
flow is controlled by the select (SEL0–SEL4)
inputs. A data-flow state is stored on the rising
edge of the clock (CLK) input if the select-enable
(SELEN
) input is low. Once a data-flow state has
been established, data is stored in the flip-flop on
the rising edge of CLK if SELEN
is high.
The data-flow control logic is designed to allow glitch-free data transmission.
The B outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω series resistors to reduce
overshoot and undershoot.
When preset (PRE
) transitions high, the outputs are disabled immediately, without waiting for a clock pulse. To
leave the high-impedance state, both PRE
and SELEN must be low and a clock pulse must be applied.
To ensure the high-impedance state during power up or power down, PRE
should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCHR162409 is characterized for operation from –40°C to 85°C.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC, UBE, and Widebus+ are trademarks of Texas Instruments Incorporated.
DGG OR DL PACKAGE
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PRE
SEL0
1A1
GND
1A2
1A3
V
CC
1A4
1A5
1A6
GND
1A7
1A8
1A9
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2A9
SEL1
SEL2
CLK
SELEN
1B1
GND
1B2
1B3
V
CC
1B4
1B5
1B6
GND
1B7
1B8
1B9
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2B9
SEL4
SEL3