Datasheet

SN74ALVC125
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES110D – JULY 1997 – REVISED DECEMBER 1998
2–47
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D Package Options Include Plastic
Small-Outline (D), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages
description
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V V
CC
operation.
The SN74ALVC125 features independent line drivers with 3-state outputs. Each output is disabled when the
associated output-enable (OE
) input is high.
To ensure the high-impedance state during power up or power down, OE
should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ALVC125 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OE A
Y
L H H
L LL
H X Z
logic symbol
†
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
EN
1
1OE
2
1A
1Y
3
4
5
2A
10
9
3A
13
12
4A
2Y
6
3Y
8
4Y
11
2OE
3OE
4OE
1
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC is a trademark of Texas Instruments Incorporated.
D, DGV, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
V
CC
4OE
4A
4Y
3OE
3A
3Y