Datasheet

SN74ALVC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCES109E JULY 1997 REVISED JANUARY 1999
239
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
D Package Options Include Plastic
Small-Outline (D), Thin Very Small-Outline
(DGV), and Thin Shrink Small-Outline (PW)
Packages
description
This dual positive-edge-triggered D-type flip-flop
is designed for 1.65-V to 3.6-V V
CC
operation.
A low level at the preset (PRE
) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE
and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input may be changed without affecting the levels at the outputs.
The SN74ALVC74 is characterized for operation from 40°C to 85°C.
FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
H LXXLH
L LXXH
H
H H HHL
H H LLH
H H L X Q
0
Q
0
This configuration is unstable; that is, it does not
persist when PRE
or CLR returns to its inactive
(high) level.
logic symbol
S
4
3
1CLK
1D
2
1D
R
1
1Q
5
6
C1
10
11
2CLK
12
2D
13
2Q
9
8
1PRE
2PRE
1CLR
2CLR
1Q
2Q
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PRODUCT PREVIEW
Copyright 1999, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
EPIC is a trademark of Texas Instruments Incorporated.
D, DGV, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q