Datasheet

SN74ALVCH32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES144A – OCTOBER 1998 – REVISED FEBRUARY 1999
3–445
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus Family
D EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
D UBT  (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Packaged in Plastic Fine-Pitch Ball Grid
Array Package
description
This 36-bit universal bus transceiver is designed for 1.65-V to 3.6-V V
CC
operation.
This device can be used as two 18-bit transceivers or one 36-bit transceiver. Data flow in each direction is
controlled by output-enable (OEAB and OEBA
), latch-enable (LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored
in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When
OEAB is low, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA
, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA
is active low).
To ensure the high-impedance state during power up or power down, OEBA
should be tied to V
CC
through a
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor
is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH32501 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
†
INPUTS
OUTPUT
OEAB LEAB CLKAB A
B
L X X X Z
H HXLL
H HXHH
H L ↑ LL
H L ↑ HH
H L L or H X B
0
‡
†
A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA
, LEBA, and CLKBA.
‡
Output level before the indicated steady-state input
conditions were established, provided that CLKAB is
high before LEAB goes low
PRODUCT PREVIEW
Copyright  1999, Texas Instruments Incorporated
EPIC, UBT, and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.