Datasheet

SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
3–425
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables (Continued)
PARITY
INPUTS
OUTPUTS
SEL OEBA OEAB ODD/EVEN
Σ OF INPUTS
A1–A8 = H
Σ OF INPUTS
B1–B8 = H
APAR BPAR APAR
ERRA
BPAR
ERRB
L H L L 0, 2, 4, 6, 8 N/A L N/A N/A H L Z
L H L L 1, 3, 5, 7 N/A L N/A N/A LHZ
L H L L 0, 2, 4, 6, 8 N/A H N/A N/A LLZ
L H L L 1, 3, 5, 7 N/A H N/A N/A HHZ
L L H L N/A 0, 2, 4, 6, 8 N/A L L Z N/A H
L L H L N/A 1, 3, 5, 7 N/A L H Z N/A L
L L H L N/A 0, 2, 4, 6, 8 N/A H L Z N/A L
L L H L N/A 1, 3, 5, 7 N/A H H Z N/A H
L H L H 0, 2, 4, 6, 8 N/A L N/A N/A L H Z
L H L H 1, 3, 5, 7 N/A L N/A N/A HLZ
L H L H 0, 2, 4, 6, 8 N/A H N/A N/A HHZ
L H L H 1, 3, 5, 7 N/A H N/A N/A LLZ
L L H H N/A 0, 2, 4, 6, 8 N/A L H Z N/A L
L L H H N/A 1, 3, 5, 7 N/A L L Z N/A H
L L H H N/A 0, 2, 4, 6, 8 N/A H H Z N/A H
L L H H N/A 1, 3, 5, 7 N/A H L Z N/A L
L H H L 0, 2, 4, 6, 8 0, 2, 4, 6, 8 L L Z H Z H
L H H L 1, 3, 5, 7 1, 3, 5, 7 L L Z LZL
L H H L 0, 2, 4, 6, 8 0, 2, 4, 6, 8 H H Z LZL
L H H L 1, 3, 5, 7 1, 3, 5, 7 H H Z HZH
L H H H 0, 2, 4, 6, 8 0, 2, 4, 6, 8 L L Z L Z L
L H H H 1, 3, 5, 7 1, 3, 5, 7 L L Z HZH
L H H H 0, 2, 4, 6, 8 0, 2, 4, 6, 8 H H Z HZH
L H H H 1, 3, 5, 7 1, 3, 5, 7 H H Z LZL
L L L L N/A N/A N/A N/A PE
†
Z PE
†
Z
L L L H N/A N/A N/A N/A PO
‡
Z PO
‡
Z
†
Parity output is set to the level so that the specific bus side is set to even parity.
‡
Parity output is set to the level so that the specific bus side is set to odd parity.