Datasheet

SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
3–424
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
FUNCTION
†
INPUTS
OUTPUT
CLKENAB OEAB LEAB CLKAB A
B
X H X X X Z
X LH XL L
X LH XH H
H LL XXB
0
‡
L LL ↑ LL
L LL ↑ HH
L LL LXB
0
‡
L L L H X B
0
§
†
A-to-B data flow is shown: B-to-A flow is similar, but uses OEBA
,
LEBA, and CLKENBA
.
‡
Output level before the indicated steady-state input conditions were
established
§
Output level before the indicated steady-state input conditions were
established, provided that CLKAB was low before LEAB went low
PARITY ENABLE
INPUTS
SEL OEBA OEAB
OPERATION OR FUNCTION
L H L Parity is checked on port A and is generated on port B.
L L H Parity is checked on port B and is generated on port A.
L H H Parity is checked on port B and port A.
L L L Parity is generated on port A and B if device is in FF mode.
H L L Q
A
data to B, Q
B
data to A
H LH
Parity functions are disabled;
Q
B
data to A
H HL
device acts as a standard
18-bit registered transceiver.
Q
A
data to B
H H H
18-bit registered transceiver.
Isolation