Datasheet
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
3–423
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus+ Family
D EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
D UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D Simultaneously Generates and Checks
Parity
D Option to Select Generate Parity and Check
or Feed-Through Data/Parity in A-to-B or
B-to-A Directions
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Packaged in Thin Shrink Small-Outline
Package
description
This 18-bit (dual-octal) noninverting registered
transceiver is designed for 1.65-V to 3.6-V V
CC
operation.
The SN74ALVCH16901 is a dual 9-bit to dual 9-bit
parity transceiver with registers. The device can
operate as a feed-through transceiver or it can
generate/check parity from the two 8-bit data
buses in either direction.
The SN74ALVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and
dual 9-bit clock-enable (CLKENAB
or CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select
(ODD/EVEN
) inputs and separate error-signal (ERRA or ERRB) outputs for checking parity. The direction of
data flow is controlled by OEAB
and OEBA. When SEL is low, the parity functions are enabled. When SEL is
high, the parity functions are disabled and the device acts as an 18-bit registered transceiver.
To ensure the high-impedance state during power up or power down, OE
should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16901 is characterized for operation from –40°C to 85°C.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1CLKENAB
LEAB
CLKAB
1ERRA
1APAR
GND
1A1
1A2
1A3
V
CC
1A4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
2A5
V
CC
2A6
2A7
2A8
GND
2APAR
2ERRA
OEAB
SEL
2CLKENAB
1CLKENBA
LEBA
CLKBA
1ERRB
1BPAR
GND
1B1
1B2
1B3
V
CC
1B4
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
2B5
V
CC
2B6
2B7
2B8
GND
2BPAR
2ERRB
OEBA
ODD/EVEN
2CLKENBA
Widebus+, EPIC, and UBT are trademarks of Texas Instruments Incorporated.