Datasheet
SN74ALVCH16843
18-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES044C – JULY 1995 – REVISED FEBRUARY 1999
3–407
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus Family
D EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 18-bit bus-interface D-type latch is designed
for 1.65-V to 3.6-V V
CC
operation.
The SN74ALVCH16843 features 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. This device is
particularly suitable for implementing buffer
registers, unidirectional bus drivers, and working
registers.
This device can be used as two 9-bit latches or
one 18-bit latch. The 18 latches are transparent
D-type latches. The device has noninverting data
(D) inputs and provides true data at its outputs.
A buffered output-enable (OE
) input can be used
to place the nine outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. The outputs also are in the
high-impedance state during power-up and
power-down conditions. The outputs remain in the
high-impedance state while the device is powered
down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The
high-impedance state and increased drive provide the capability to drive bus lines without need for interface
or pullup components.
The output-enable (OE
) input does not affect the internal operations of the latch. Previously stored data can be
retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE
should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating inputs at a valid logic level.
The SN74ALVCH16843 is characterized for operation from –40°C to 85°C.
PRODUCT PREVIEW
Copyright 1999, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1CLR
1OE
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
V
CC
2Q7
2Q8
GND
2Q9
2OE
2CLR
1LE
1PRE
1D1
GND
1D2
1D3
V
CC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
V
CC
2D7
2D8
GND
2D9
2PRE
2LE
EPIC and Widebus are trademarks of Texas Instruments Incorporated.