Datasheet

SN74ALVCH16828
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES042B JULY 1995 REVISED FEBRUARY 1999
3315
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus Family
D EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 20-bit inverting buffer/driver is designed for
1.65-V to 3.6-V V
CC
operation.
The SN74ALVCH16828 is composed of two 10-bit
sections with separate output-enable signals. For
either 10-bit buffer section, the two output-enable
(1OE1
and 1OE2 or 2OE1 and 2OE2) inputs must
both be low for the corresponding Y outputs to be
active. If either output-enable input is high, the
outputs of that 10-bit buffer section are in the
high-impedance state.
To ensure the high-impedance state during power
up or power down, OE
should be tied to V
CC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold
unused or floating inputs at a valid logic level.
The SN74ALVCH16828 is characterized for
operation from 40°C to 85°C.
FUNCTION TABLE
(each 10-bit section)
INPUTS
OUTPUT
OE1 OE2
A
Y
L L L H
L LH L
H XX Z
X H X Z
PRODUCT PREVIEW
Copyright 1999, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
DGG OR DL PACKAGE
(TOP VIEW)
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1OE1
1Y1
1Y2
GND
1Y3
1Y4
V
CC
1Y5
1Y6
1Y7
GND
1Y8
1Y9
1Y10
2Y1
2Y2
2Y3
GND
2Y4
2Y5
2Y6
V
CC
2Y7
2Y8
GND
2Y9
2Y10
2OE1
1OE2
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
1A7
GND
1A8
1A9
1A10
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2A9
2A10
2OE2
EPIC and Widebus are trademarks of Texas Instruments Incorporated.