Datasheet
SN74ALVCH16652
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS
SCES034A – JULY 1995 – REVISED FEBRUARY 1999
3–251
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus Family
D EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 16-bit bus transceiver and register is
designed for 1.65-V to 3.6-V V
CC
operation.
The SN74ALVCH16652 consists of D-type
flip-flops and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
The device can be used as two 8-bit transceivers
or one 16-bit transceiver.
Complementary output-enable (OEAB and
OEBA
) inputs are provided to control the
transceiver functions. Select-control (SAB and
SBA) inputs are provided to select whether
real-time or stored data is transferred. A low input
level selects real-time data, and a high input level
selects stored data. The circuitry used for select
control eliminates the typical decoding glitch that
occurs in a multiplexer during the transition
between stored and real-time data. Figure 1
illustrates the four fundamental bus-management
functions that can be performed with the
SN74ALVCH16652.
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs regardless of the levels on the select-control or output-enable
inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using the
internal D-type flip-flops by simultaneously enabling OEAB and OEBA
. In this configuration, each output
reinforces its input. Thus, when all other data sources to the two sets of bus line are in the high-impedance state,
each set of bus lines remains at its last level configuration.
Active bus-hold circuitry is provided to hold unused for floating inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OEBA should be tied to V
CC
through a
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor
is determined by the current-sinking current-sourcing capability of the driver.
The SN74ALVCH16652 is characterized for operation from –40°C to 85°C.
PRODUCT PREVIEW
Copyright 1999, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
DGG OR DL PACKAGE
(TOP VIEW)
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1OEAB
1CLKAB
1SAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2SAB
2CLKAB
2OEAB
1OEBA
1CLKBA
1SBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2SBA
2CLKBA
2OEBA
EPIC and Widebus are trademarks of Texas Instruments Incorporated.