Datasheet
SN74ALVCH16280
16-BIT TO 32-BIT REGISTERED BUS EXCHANGER
WITH BYTE MASKS AND 3-STATE OUTPUTS
SCES033A – JULY 1995 – REVISED FEBRUARY 1999
3–85
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus Family
D EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Packaged in Thin Shrink Small-Outline
Package
description
This 16-bit to 32-bit registered bus exchanger is
designed for 1.65-V to 3.6-V V
CC
operation. This
device is intended for use in applications where
data must be transferred from a narrow
high-speed bus to a wide lower-frequency bus.
The device provides synchronous data exchange
between the A and B ports. Data is stored in the
internal registers on the low-to-high transition of
the clock (CLK) input. For data transfer in the
B-to-A direction, SEL
selects 1B or 2B data for the
A outputs.
For data transfer in the A-to-B direction, a
two-stage pipeline is provided in the 1B path, and
a single storage register in the 2B path. Data flow
is controlled by the active-low output enable (OE
)
and the direction-control (DIR) input. DIR is
registered to synchronize the bus direction
changes with the clock.
Two mask bits are provided for both data bytes.
The D outputs are controlled by the active-low OE
.
To ensure the high-impedance state during power
up or power down, OE
should be tied to V
CC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold
unused or floating data inputs at a valid logic level.
The SN74ALVCH16280 is characterized for
operation from –40°C to 85°C.
PRODUCT PREVIEW
Copyright 1999, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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V
CC
GND
2B7
1B7
2B6
GND
1B6
2B5
1B5
V
CC
2B4
1B4
2B3
1B3
GND
2B2
1B2
2B1
1B1
V
CC
GND
2D2
1D2
2D1
1D1
V
CC
C1
C2
A1
GND
A2
A3
A4
V
CC
A5
A6
A7
GND
CLK
SEL
V
CC
GND
1B8
2B8
1B9
GND
2B9
1B10
2B10
V
CC
1B11
2B11
1B12
2B12
GND
1B13
2B13
1B14
2B14
V
CC
GND
1B15
2B15
1B16
2B16
V
CC
A16
A15
A14
GND
A13
A12
A11
V
CC
A10
A9
A8
GND
OE
DIR
DBB PACKAGE
(TOP VIEW)
EPIC and Widebus are trademarks of Texas Instruments Incorporated.