Datasheet
SN74ALVCH16271
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES017E – JULY 1995 – REVISED FEBRUARY 1999
3–65
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Member of the Texas Instruments
Widebus Family
D EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 12-bit to 24-bit bus exchanger is designed for
1.65-V to 3.6-V V
CC
operation.
The SN74ALVCH16271 is intended for
applications in which two separate data paths
must be multiplexed onto, or demultiplexed from,
a single data path. This device is particularly
suitable as an interface between conventional
DRAMs and high-speed microprocessors.
A data is stored in the internal A-to-B registers on
the low-to-high transition of the clock (CLK) input,
provided that the clock-enable (CLKENA
) inputs
are low. Proper control of these inputs allows two
sequential 12-bit words to be presented as a
24-bit word on the B port.
Transparent latches in the B-to-A path allow asynchronous operation to maximize memory access throughput.
These latches transfer data when the latch-enable (LE
) inputs are low. The select (SEL) line selects 1B or 2B
data for the A outputs. Data flow is controlled by the active-low output enables (OEA
, OEB).
To ensure the high-impedance state during power up or power down, the output enables should be tied to V
CC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16271 is characterized for operation from –40°C to 85°C.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
DGG OR DL PACKAGE
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OEA
LE1B
2B3
GND
2B2
2B1
V
CC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
V
CC
1B1
1B2
GND
1B3
LE2B
SEL
OEB
CLKENA2
2B4
GND
2B5
2B6
V
CC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
V
CC
1B6
1B5
GND
1B4
CLKENA1
CLK