Datasheet

GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
1–7
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t
PLH
Propagation delay time, low-to-high level output
The time between the specified reference points on the input and output voltage waveforms with the
output changing from the defined low level to the defined high level
t
PLZ
Disable time (of a 3-state output) from low level
The time interval between the specified reference points on the input and the output voltage waveforms
with the 3-state output changing from the defined low level to the high-impedance (off) state
t
PZH
Enable time (of a 3-state output) to high level
The time interval between the specified reference points on the input and output voltage waveforms with
the 3-state output changing from the high-impedance (off) state to the defined high level
t
PZL
Enable time (of a 3-state output) to low level
The time interval between the specified reference points on the input and output voltage waveforms with
the 3-state output changing from the high-impedance (off) state to the defined low level
t
sk(o)
Output skew
The difference between any two propagation delay times when a single switching input or multiple inputs
switching simultaneously cause multiple outputs to switch, as observed across all switching output. This
parameter is used to describe the fanout capability of a clock driver and is of concern when making
decisions on clock buffering and distribution networks.
t
su
Setup time
The time interval between the application of a signal at a specified input terminal and a subsequent active
transition at another specified input terminal
NOTES: 1. The setup time is the actual time interval between two signal events and is determined by
the system in which the digital circuit operates. A minimum value is specified that is the shortest
interval for which correct operation of the digital circuit is to be expected.
2. The setup time may have a negative value, in which case the minimum limit defines the
longest interval (between the active transition and the application of the other signal) for which
correct operation of the digital circuit is to be expected.
t
w
Pulse duration (width)
The time interval between specified reference points on the leading and trailing edges of the
pulse waveform
V
IH
High-level input voltage
An input voltage within the more positive (less negative) of the two ranges of values used to represent
the binary variables
NOTE: A minimum is specified that is the least-positive value of high-level input voltage for which
operation of the logic element within specification limits is to be expected.
V
IL
Low-level input voltage
An input voltage within the less positive (more negative) of the two ranges of values used to represent
the binary variables
NOTE: A maximum is specified that is the most-positive value of low-level input voltage for which
operation of the logic element within specification limits is to be expected.
V
OH
High-level output voltage
The voltage at an output terminal with input conditions applied that, according to product specification,
establishes a high level at the output