Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICs74ALVCHR SSOP 56

General Information

ALVC Gates/Octals

ALVC Widebus/Widebus+

ALVC Widebus With Series Damping Resistors

ALVC Dual-Supply-Voltage Translators

SSTL

HSTL

ALB

Mechanical Data

Output Derating Curves

Summary of content (872 pages)

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General Information ALVC Gates/Octals ALVC Widebus/Widebus+ ALVC Widebus With Series Damping Resistors ALVC Dual-Supply-Voltage Translators SSTL HSTL ALB Mechanical Data Output Derating Curves A
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ALVC Advanced Low-Voltage CMOS Data Book Including SSTL, HSTL, and ALB Printed on Recycled Paper
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete.
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INTRODUCTION Since its inception in 1994, the Texas Instruments (TI) ALVC (Advanced Low-Voltage CMOS) logic family has been the de facto standard for high-performance low-voltage logic. Designed for operation in the 2.3-V to 3.6-V VCC range, the close to 80 functions of the ALVC family allow the design flexibility and ease needed for today’s most demanding high-performance systems. For bus-interface functions, ALVC offers a current drive of 24 mA and static power consumption of 40 µA.
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PRODUCT STAGE STATEMENTS Product stage statements are used on Texas Instruments data sheets to indicate the development stage(s) of the product(s) specified in the data sheets. If all products specified in a data sheet are at the same development stage, the appropriate statement from the following list is placed in the lower left corner of the first page of the data sheet. PRODUCTION DATA information is current as of publication date.
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General Information ALVC Gates/Octals ALVC Widebus/Widebus+ ALVC Widebus With Series Damping Resistors ALVC Dual-Supply-Voltage Translators SSTL HSTL ALB Mechanical Data A Output Derating Curves 1–1
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Contents General Information Page Alphanumeric Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5 Explanation of Function Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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ALPHANUMERIC INDEX DEVICE PAGE SN74ALB16244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3 SN74ALB16245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–9 SN74ALVC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 SN74ALVC04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9 SN74ALVC08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15 SN74ALVC10 . . . . . . . . . . . . . .
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GLOSSARY SYMBOLS, TERMS, AND DEFINITIONS INTRODUCTION These symbols, terms, and definitions are in accordance with those currently agreed upon by the JEDEC Council of the Electronic Industries Association (EIA) for use in the USA and by the International Electrotechnical Commission (IEC) for international use.
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GLOSSARY SYMBOLS, TERMS, AND DEFINITIONS IOL IOZ, IOZPU/PD Low-level output current The current into* an output with input conditions applied that, according to the product specification, establishes a low level at the output Off-state (high-impedance-state) output current (of a 3-state output) The current flowing into* an output having 3-state capability with input conditions established that, according to the product specification, establishes the high-impedance state at the output ta Access time The
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GLOSSARY SYMBOLS, TERMS, AND DEFINITIONS tPLH Propagation delay time, low-to-high level output The time between the specified reference points on the input and output voltage waveforms with the output changing from the defined low level to the defined high level tPLZ Disable time (of a 3-state output) from low level The time interval between the specified reference points on the input and the output voltage waveforms with the 3-state output changing from the defined low level to the high-impedance (off)
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GLOSSARY SYMBOLS, TERMS, AND DEFINITIONS VOL Low-level output voltage The voltage at an output terminal with input conditions applied that, according to product specification, establishes a low level at the output VIT+ Positive-going input threshold level The voltage level at a transition-operated input that causes operation of the logic element according to specification as the input voltage rises from a level below the negative-going threshold voltage, VIT– VIT– Negative-going input threshold level T
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EXPLANATION OF FUNCTION TABLES The following symbols are used in function tables on TI data sheets: H L ↑ ↓ X Z a...
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EXPLANATION OF FUNCTION TABLES Among the most complex function tables are those of the shift registers. These embody most of the symbols used in any of the function tables, plus more. Below is the function table of a 4-bit bidirectional universal shift register.
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D-TYPE FLIP-FLOP AND LATCH SIGNAL CONVENTIONS It is normal TI practice to name the outputs and other inputs of a D-type flip-flop or latch and to draw its logic symbol based on the assumption of true data (D) inputs. Outputs that produce data in phase with the data inputs are called Q and those producing complementary data are called Q. An input that causes a Q output to go high or a Q output to go low is called preset (PRE).
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DEVICE NAMES AND PACKAGE DESIGNATORS Example: SN 74 1 2 1 H 16 2 244 3 4 5 6 7 Standard Prefix Example: 2 ALVC 6 SNJ – Conforms to MIL-PRF-38535 (QML) Temperature Range Examples: 54 – Military 74 – Commercial 3 Examples: Blank – Transistor-Transistor Logic ABT – Advanced BiCMOS Technology ABTE – Advanced BiCMOS Technology/ Enhanced Transceiver Logic AC/ACT – Advanced CMOS Logic AHC/AHCT – Advanced High-Speed CMOS Logic ALB – Advanced Low-Voltage BiCMOS ALS – Advanced Low-Power Schot
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DEVICE NAMES AND PACKAGE DESIGNATORS NOTIFICATION OF PACKAGE NOMENCLATURE ALIAS (for Standard Linear and Logic device names of greater than 18 characters) TI is converting from its current order-entry system to a more advanced system. This conversion requires modifications, both internal and external, to TI’s current business processes. This new system will ultimately provide significant improvements to all facets of TI’s business – from production, to order entry, to logistics.
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General Information ALVC Gates/Octals ALVC Widebus/Widebus+ ALVC Widebus With Series Damping Resistors ALVC Dual-Supply-Voltage Translators SSTL HSTL ALB Mechanical Data A Output Derating Curves 2–1
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Contents Page ALVC Gates/Octals SN74ALVC00 SN74ALVC04 SN74ALVC08 SN74ALVC10 SN74ALVC14 SN74ALVC32 SN74ALVC74 SN74ALVC125 SN74ALVC126 SN74ALVC244 SN74ALVCH244 SN74ALVC245 SN74ALVCH245 SN74ALVCH373 SN74ALVCH374 2–2 Quadruple 2-Input Positive-NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hex Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quadruple 2-Input Positive-AND Gate . . . . .
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SN74ALVC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCES115C – JULY 1997 – REVISED AUGUST 1998 D EPIC (Enhanced-Performance Implanted D D D D, DGV, OR PW PACKAGE (TOP VIEW) CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Small-Outline (D), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages 1A 1B 1Y 2A 2B 2Y GND 1
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SN74ALVC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCES115C – JULY 1997 – REVISED AUGUST 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
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SN74ALVC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCES115C – JULY 1997 – REVISED AUGUST 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA VOL ∆ICC Ci UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.6 V ±5 µA 3.
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SN74ALVC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCES115C – JULY 1997 – REVISED AUGUST 1998 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.
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SN74ALVC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCES115C – JULY 1997 – REVISED AUGUST 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
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SN74ALVC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCES115C – JULY 1997 – REVISED AUGUST 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
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SN74ALVC04 HEX INVERTER SCES117F – JULY 1997 – REVISED FEBRUARY 1999 D EPIC (Enhanced-Performance Implanted D D D D, DGV, OR PW PACKAGE (TOP VIEW) CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Small-Outline (D), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages 1A 1Y 2A 2Y 3A 3Y GND 1 14 2 13 3 12 4 1
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SN74ALVC04 HEX INVERTER SCES117F – JULY 1997 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
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SN74ALVC04 HEX INVERTER SCES117F – JULY 1997 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA VOL ∆ICC Ci UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
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SN74ALVC04 HEX INVERTER SCES117F – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
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SN74ALVC04 HEX INVERTER SCES117F – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
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SN74ALVC04 HEX INVERTER SCES117F – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) 2.7 V 1.
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SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCES101D – JULY 1997 – REVISED AUGUST 1998 D EPIC (Enhanced-Performance Implanted D D D D, DGV, OR PW PACKAGE (TOP VIEW) CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Small-Outline (D), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages 1A 1B 1Y 2A 2B 2Y GND 1 1
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SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCES101D – JULY 1997 – REVISED AUGUST 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
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SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCES101D – JULY 1997 – REVISED AUGUST 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA VOL ∆ICC Ci UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
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SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCES101D – JULY 1997 – REVISED AUGUST 1998 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.
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SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCES101D – JULY 1997 – REVISED AUGUST 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
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SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCES101D – JULY 1997 – REVISED AUGUST 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input tsu 0V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0V tPLH 2.7 V 1.5 V VOH 1.5 V VOL 1.
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SN74ALVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE SCES106D – JULY 1997 – REVISED OCTOBER 1998 D EPIC (Enhanced-Performance Implanted D D D D, DGV, OR PW PACKAGE (TOP VIEW) CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Small-Outline (D), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages 1A 1B 2A 2B 2C 2Y GND 1 14
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SN74ALVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE SCES106D – JULY 1997 – REVISED OCTOBER 1998 logic diagram, each gate (positive logic) A Y B C absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SN74ALVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE SCES106D – JULY 1997 – REVISED OCTOBER 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA VOL ∆ICC Ci UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.6 V ±5 µA 3.
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SN74ALVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE SCES106D – JULY 1997 – REVISED OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.
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SN74ALVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE SCES106D – JULY 1997 – REVISED OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
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SN74ALVC10 TRIPLE 3-INPUT POSITIVE-NAND GATE SCES106D – JULY 1997 – REVISED OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0V tPLH tPHL VOH 1.5 V 2.
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SN74ALVC14 HEX SCHMITT-TRIGGER INVERTER SCES107D – JULY 1997 – REVISED JANUARY 1999 D EPIC (Enhanced-Performance Implanted D D, DGV, OR PW PACKAGE (TOP VIEW) CMOS) Submicron Process Package Options Include Plastic Small-Outline (D), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages 1A 1Y 2A 2Y 3A 3Y GND description This hex Schmitt-trigger inverter is designed for 1.65-V to 3.6-V VCC operation.
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SN74ALVC14 HEX SCHMITT-TRIGGER INVERTER SCES107D – JULY 1997 – REVISED JANUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.
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SN74ALVC14 HEX SCHMITT-TRIGGER INVERTER SCES107D – JULY 1997 – REVISED JANUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TYP† VCC 1.65 V MIN 2.7 V 0.8 2 3V 0.8 2 3.6 V 0.8 2 2.7 V 0.4 1.4 3V 0.6 1.5 3.6 V 0.8 1.8 2.7 V 0.3 1.1 3V 0.3 1.2 3.6 V 0.3 1.2 1.65 V to 3.6 V VCC–0.2 1.2 VT+ Positive-going threshold MAX UNIT V 1.65 V VT– Negative-going threshold V 1.
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SN74ALVC14 HEX SCHMITT-TRIGGER INVERTER SCES107D – JULY 1997 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
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SN74ALVC14 HEX SCHMITT-TRIGGER INVERTER SCES107D – JULY 1997 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V From Output Under Test 2 × VCC S1 500 Ω Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.
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SN74ALVC14 HEX SCHMITT-TRIGGER INVERTER SCES107D – JULY 1997 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V 0V 0V tsu PRODUCT PREVIEW 1.5 V Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
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SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCES108D – JULY 1997 – REVISED AUGUST 1998 D EPIC (Enhanced-Performance Implanted D D D D, DGV, OR PW PACKAGE (TOP VIEW) CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Small-Outline (D), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages 1A 1B 1Y 2A 2B 2Y GND 1 14
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SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCES108D – JULY 1997 – REVISED AUGUST 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
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SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCES108D – JULY 1997 – REVISED AUGUST 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA VOL ∆ICC Ci UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
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SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCES108D – JULY 1997 – REVISED AUGUST 1998 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.
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SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCES108D – JULY 1997 – REVISED AUGUST 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
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SN74ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE SCES108D – JULY 1997 – REVISED AUGUST 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
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SN74ALVC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES109E – JULY 1997 – REVISED JANUARY 1999 D EPIC (Enhanced-Performance Implanted D D, DGV, OR PW PACKAGE (TOP VIEW) CMOS) Submicron Process Package Options Include Plastic Small-Outline (D), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages 1CLR 1D 1CLK 1PRE 1Q 1Q GND description This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.
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SN74ALVC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES109E – JULY 1997 – REVISED JANUARY 1999 logic diagram, each flip-flop (positive logic) PRE CLK C C C Q TG C C C C D TG TG TG C C C Q PRODUCT PREVIEW CLR absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 58
SN74ALVC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES109E – JULY 1997 – REVISED JANUARY 1999 recommended operating conditions (see Note 4) VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MAX 1.65 3.6 V 1.7 2 0.35 × VCC 0.8 VCC VCC 0 VCC = 1.65 V VCC = 2.3 V V V –4 –12 VCC = 2.7 V VCC = 3 V mA –12 –24 VCC = 1.
PAGE 59
SN74ALVC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES109E – JULY 1997 – REVISED JANUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock Clock frequency tw Pulse duration tsu Setup time th Hold time MAX VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.
PAGE 60
SN74ALVC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES109E – JULY 1997 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 61
SN74ALVC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES109E – JULY 1997 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 62
SN74ALVC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES109E – JULY 1997 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 500 Ω From Output Under Test 6V Open S1 GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V 1.5 V Input 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 63
SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110D – JULY 1997 – REVISED DECEMBER 1998 D EPIC (Enhanced-Performance Implanted D D D D, DGV, OR PW PACKAGE (TOP VIEW) CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Small-Outline (D), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages 1OE 1A 1Y 2OE
PAGE 64
SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110D – JULY 1997 – REVISED DECEMBER 1998 logic diagram (positive logic) 1OE 1A 2OE 2A 1 2 3OE 3 1Y 4 5 3A 4OE 6 2Y 4A 10 9 8 3Y 13 12 11 4Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . .
PAGE 65
SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110D – JULY 1997 – REVISED DECEMBER 1998 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.7 V VCC = 3 V V 0.
PAGE 66
SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110D – JULY 1997 – REVISED DECEMBER 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA IOH = –4 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA Ci Control inputs Data inputs 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 VI = VCC or GND V 3V 0.55 3.6 V ±5 µA 3.6 V ±10 µA 3.6 V 10 µA 3 V to 3.
PAGE 67
SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110D – JULY 1997 – REVISED DECEMBER 1998 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.
PAGE 68
SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110D – JULY 1997 – REVISED DECEMBER 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 69
SN74ALVC125 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES110D – JULY 1997 – REVISED DECEMBER 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0V tPLH tPHL VOH 1.5 V 2.
PAGE 70
SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111E – JULY 1997 – REVISED FEBRUARY 1999 D EPIC  (Enhanced-Performance Implanted D D D D, DGV, OR PW PACKAGE (TOP VIEW) CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Small-Outline (D), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages 1OE 1A 1Y 2O
PAGE 71
SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111E – JULY 1997 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1OE 1A 2OE 2A 1 2 3OE 3 1Y 4 5 3A 4OE 6 2Y 4A 10 9 8 3Y 13 12 11 4Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . .
PAGE 72
SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111E – JULY 1997 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 73
SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111E – JULY 1997 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA IOH = –4 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA Ci Control inputs Data inputs 2.3 V 1.7 2.7 V 2.2 UNIT 3V 2.4 3V 2 V 0.2 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 IO = 0 Other inputs at VCC or GND One input at VCC – 0.6 V, 2 0.
PAGE 74
SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111E – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.
PAGE 75
SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111E – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 76
SN74ALVC126 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES111E – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 500 Ω From Output Under Test 6V Open S1 GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 2.7 V 0V Output Control 1.5 V 1.
PAGE 77
SN74ALVC244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES188 – FEBRUARY 1999 D EPIC (Enhanced-Performance Implanted D D D DGV, DW, NS, OR PW PACKAGE (TOP VIEW) CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Small-Outline (DW, NS), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A
PAGE 78
SN74ALVC244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES188 – FEBRUARY 1999 logic symbol† 1OE 1A1 1A2 1A3 1A4 1 EN 2OE 18 2 4 16 6 14 12 8 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 19 EN 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PAGE 79
SN74ALVC244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES188 – FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.7 V VCC = 3 V Input transition rise or fall rate V 0.
PAGE 80
SN74ALVC244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES188 – FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA VO = VCC or GND VI = VCC or GND, Ci One input at VCC – 0.6 V, Control inputs Data inputs 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 2.3 V 0.4 2.3 V 0.7 2.7 V 0.
PAGE 81
SN74ALVC244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES188 – FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.
PAGE 82
SN74ALVC244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES188 – FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 83
SN74ALVC244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES188 – FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0V tPLH tPHL VOH 1.5 V 2.
PAGE 84
SN74ALVCH244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES112C – JULY 1997 – REVISED FEBRUARY 1999 D EPIC (Enhanced-Performance Implanted D D D D DGV, DW, NS, OR PW PACKAGE (TOP VIEW) CMOS) Submicron Process Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Small-Outline (DW, NS),
PAGE 85
SN74ALVCH244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES112C – JULY 1997 – REVISED FEBRUARY 1999 logic symbol† 1OE 1A1 1A2 1A3 1A4 1 EN 2OE 18 2 4 16 6 14 12 8 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 19 EN 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PAGE 86
SN74ALVCH244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES112C – JULY 1997 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 87
SN74ALVCH244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES112C – JULY 1997 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.
PAGE 88
SN74ALVCH244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES112C – JULY 1997 – REVISED FEBRUARY 1999 operating characteristics, TA = 25°C TEST CONDITIONS PARAMETER Cpd Power dissipation capacitance per buffer/driver Outputs enabled Outputs disabled VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V TYP † TYP TYP 22 28 † 1.5 4 VCC = 1.8 V CL = 0, f = 10 MHz UNIT pF † This information was not available at the time of publication.
PAGE 89
SN74ALVCH244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES112C – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 90
SN74ALVCH244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES112C – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 91
SN74ALVCH244 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES112C – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 92
SN74ALVC245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES271A – APRIL 1999 – REVISED MAY 1999 D EPIC (Enhanced-Performance Implanted D D DGV, DW, OR PW PACKAGE (TOP VIEW) CMOS) Submicron Process Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Small-Outline (DW), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages DIR A1 A2 A3 A4 A5 A6 A7 A8 GND description This octal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
PAGE 93
SN74ALVC245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES271A – APRIL 1999 – REVISED MAY 1999 logic symbol† 19 OE 1 DIR 2 A1 G3 3 EN1 [BA] 3 EN2 [AB] 18 1 B1 2 A2 A3 A4 A5 A6 A7 A8 3 17 4 16 5 15 6 14 7 13 8 12 9 11 B2 B3 B4 B5 B6 B7 B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PAGE 94
SN74ALVC245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES271A – APRIL 1999 – REVISED MAY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 95
SN74ALVC245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES271A – APRIL 1999 – REVISED MAY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA VO = VCC or GND VI = VCC or GND, One input at VCC – 0.6 V, Ci Control inputs Cio A or B ports 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 2.3 V 0.
PAGE 96
SN74ALVC245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES271A – APRIL 1999 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.
PAGE 97
SN74ALVC245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES271A – APRIL 1999 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 98
SN74ALVC245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES271A – APRIL 1999 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 99
SN74ALVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES119D – JULY 1997 – REVISED MAY 1999 D EPIC (Enhanced-Performance Implanted D D D DGV, DW, OR PW PACKAGE (TOP VIEW) CMOS) Submicron Process Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic Small-Outline (DW), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages DIR A1 A2 A3 A4 A5 A6 A7 A8 GND descrip
PAGE 100
SN74ALVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES119D – JULY 1997 – REVISED MAY 1999 logic symbol† 19 OE 1 DIR 2 A1 G3 3 EN1 [BA] 3 EN2 [AB] 18 1 B1 2 A2 A3 A4 A5 A6 A7 A8 3 17 4 16 5 15 6 14 7 13 8 12 9 11 B2 B3 B4 B5 B6 B7 B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PAGE 101
SN74ALVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES119D – JULY 1997 – REVISED MAY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 102
SN74ALVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES119D – JULY 1997 – REVISED MAY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 103
SN74ALVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES119D – JULY 1997 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.
PAGE 104
SN74ALVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES119D – JULY 1997 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 105
SN74ALVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES119D – JULY 1997 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 106
SN74ALVCH373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES116D – JULY 1997 – REVISED JANUARY 1999 D EPIC (Enhanced-Performance Implanted D D DGV, DW, OR PW PACKAGE (TOP VIEW) CMOS) Submicron Process Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic Small-Outline (DW), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND description This octal transparent D-type latch is desi
PAGE 107
SN74ALVCH373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES116D – JULY 1997 – REVISED JANUARY 1999 logic symbol† 1 OE LE 1D 2D 3D 4D 5D 6D 7D 8D 11 3 EN C1 2 1D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PAGE 108
SN74ALVCH373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES116D – JULY 1997 – REVISED JANUARY 1999 recommended operating conditions (see Note 4) VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 109
SN74ALVCH373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES116D – JULY 1997 – REVISED JANUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA PRODUCT PREVIEW UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 110
SN74ALVCH373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES116D – JULY 1997 – REVISED JANUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) PARAMETER tpd FROM (INPUT) TO (OUTPUT) VCC = 1.8 V TYP VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.
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SN74ALVCH373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES116D – JULY 1997 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
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SN74ALVCH373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES116D – JULY 1997 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC VCC/2 0V 0V tsu VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH VCC/2 VCC VCC/2 tPLZ VCC VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.
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SN74ALVCH373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES116D – JULY 1997 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 0V 1.5 V 0V tsu PRODUCT PREVIEW 1.5 V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 2.
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SN74ALVCH374 OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES118D – JULY 1997 – REVISED JANUARY 1999 D EPIC (Enhanced-Performance Implanted D D DGV, DW, OR PW PACKAGE (TOP VIEW) CMOS) Submicron Process Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic Small-Outline (DW), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND description This octal edge-triggered D
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SN74ALVCH374 OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES118D – JULY 1997 – REVISED JANUARY 1999 logic symbol† 1 OE CLK 1D 2D 3D 4D 5D 6D 7D 8D 11 3 EN C1 2 1D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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SN74ALVCH374 OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES118D – JULY 1997 – REVISED JANUARY 1999 recommended operating conditions (see Note 4) VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
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SN74ALVCH374 OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES118D – JULY 1997 – REVISED JANUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA PRODUCT PREVIEW UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.
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SN74ALVCH374 OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES118D – JULY 1997 – REVISED JANUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V TYP VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.
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SN74ALVCH374 OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES118D – JULY 1997 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
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SN74ALVCH374 OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES118D – JULY 1997 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
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SN74ALVCH374 OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES118D – JULY 1997 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V 1.5 V 0V 1.5 V 0V tsu PRODUCT PREVIEW Input VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
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General Information ALVC Gates/Octals ALVC Widebus/Widebus+ ALVC Widebus With Series Damping Resistors ALVC Dual-Supply-Voltage Translators SSTL HSTL ALB Mechanical Data A Output Derating Curves 3–1
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Contents Page ALVC Widebus /Widebus+ SN74ALVCH16240 SN74ALVC16244A SN74ALVCH16244 SN74ALVCH16245 SN74ALVCH16260 SN74ALVCH16269 SN74ALVCH16270 SN74ALVCH16271 SN74ALVCH16272 SN74ALVCH16280 SN74ALVCH16282 SN74ALVC16334 SN74ALVCH16334 SN74ALVCH16344 SN74ALVCH16373 SN74ALVCH16374 SN74ALVCH16409 SN74ALVCH16500 SN74ALVCH16501 SN74ALVCH16524 SN74ALVCH16525 SN74ALVCH16540 SN74ALVCH16541 SN74ALVCH16543 SN74ALVCH16600 SN74ALVCH16601 SN74ALVCH16646 SN74ALVCH16652 SN74ALVCH16721 SN74ALVCH16820 SN74ALVCH16821 SN74ALV
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SN74ALVCH16240 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES045C – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package O
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SN74ALVCH16240 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES045C – JULY 1995 – REVISED FEBRUARY 1999 logic symbol† 1OE 2OE 3OE 4OE 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1 EN1 48 25 24 EN2 EN3 EN4 47 1 1 46 3 44 5 43 6 41 1 2 8 40 9 38 11 37 12 36 1 3 13 35 14 33 16 32 17 30 19 1 4 29 20 27 22 26 23 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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SN74ALVCH16240 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES045C – JULY 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 1 3OE 47 2 46 3 44 5 43 6 1Y1 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 48 4OE 41 8 40 9 38 11 37 12 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 25 36 13 35 14 33 16 32 17 3Y1 3Y2 3Y3 3Y4 24 30 19 29 20 27 22 26 23 4Y1 4Y2 4Y3 4Y4 absolute maximum ratings over operating free-air temperature
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SN74ALVCH16240 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES045C – JULY 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
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SN74ALVCH16240 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES045C – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
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SN74ALVCH16240 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES045C – JULY 1995 – REVISED FEBRUARY 1999 operating characteristics, TA = 25°C PARAMETER Outputs enabled Power dissipation capacitance Cpd VCC = 1.8 V TYP † TEST CONDITIONS CL = 50 pF, Outputs disabled f = 10 MHz VCC = 2.5 V TYP VCC = 3.3 V TYP 16 19 4 5 † UNIT pF † This information was not available at the time of publication. PARAMETER MEASUREMENT INFORMATION VCC = 1.
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SN74ALVCH16240 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES045C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
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SN74ALVCH16240 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES045C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0V tPLH 1.5 V 1.5 V VOL tPLZ 3V 1.
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SN74ALVC16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS250G – JANUARY 1993 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC  ( Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Ou
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SN74ALVC16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS250G – JANUARY 1993 – REVISED FEBRUARY 1999 logic symbol† 1OE 2OE 1 EN1 48 25 3OE 4OE 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 24 EN2 EN3 EN4 47 1 1 46 3 44 5 43 6 41 40 1 2 8 9 38 11 37 12 36 13 35 1 3 14 33 16 32 17 30 1 4 19 29 20 27 22 26 23 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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SN74ALVC16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS250G – JANUARY 1993 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 1 3OE 47 2 46 3 44 5 43 6 1Y1 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 48 4OE 41 8 40 9 38 11 37 12 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 25 36 13 35 14 33 16 32 17 3Y1 3Y2 3Y3 3Y4 24 30 19 29 20 27 22 26 23 4Y1 4Y2 4Y3 4Y4 absolute maximum ratings over operating free-air temperatu
PAGE 135
SN74ALVC16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS250G – JANUARY 1993 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
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SN74ALVC16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS250G – JANUARY 1993 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA VO = VCC or GND VI = VCC or GND, Ci IO = 0 Other inputs at VCC or GND One input at VCC – 0.6 V, Control inputs Data inputs UNIT VCC–0.2 1.2 2.3 V 2 2.
PAGE 137
SN74ALVC16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS250G – JANUARY 1993 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
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SN74ALVC16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS250G – JANUARY 1993 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 139
SN74ALVC16244A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS250G – JANUARY 1993 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
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SN74ALVCH16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES014E – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Pack
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SN74ALVCH16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES014E – JULY 1995 – REVISED FEBRUARY 1999 logic symbol† 1OE 2OE 1 EN1 48 25 3OE 4OE 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 24 EN2 EN3 EN4 47 1 1 46 3 44 5 43 6 41 40 1 2 8 9 38 11 37 12 36 13 35 1 3 14 33 16 32 17 30 1 4 19 29 20 27 22 26 23 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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SN74ALVCH16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES014E – JULY 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 1 3OE 47 2 46 3 44 5 43 6 1Y1 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 48 4OE 41 8 40 9 38 11 37 12 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 25 36 13 35 14 33 16 32 17 3Y1 3Y2 3Y3 3Y4 24 30 19 29 20 27 22 26 23 4Y1 4Y2 4Y3 4Y4 absolute maximum ratings over operating free-air temperature
PAGE 143
SN74ALVCH16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES014E – JULY 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 144
SN74ALVCH16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES014E – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 145
SN74ALVCH16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES014E – JULY 1995 – REVISED FEBRUARY 1999 operating characteristics, TA = 25°C PARAMETER Outputs enabled Power dissipation capacitance Cpd VCC = 1.8 V TYP † TEST CONDITIONS CL = 50 pF, Outputs disabled f = 10 MHz VCC = 2.5 V TYP VCC = 3.3 V TYP 16 19 4 5 † UNIT pF † This information was not available at the time of publication. PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 146
SN74ALVCH16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES014E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 147
SN74ALVCH16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES014E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V 1.5 V 0V tPLH 1.5 V 2.
PAGE 148
SN74ALVCH16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES015F – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Pa
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SN74ALVCH16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES015F – JULY 1995 – REVISED FEBRUARY 1999 logic symbol† 48 1OE 1DIR G3 1 3 EN1 [BA] 3 EN2 [AB] 25 2OE 2DIR G6 24 6 EN4 [BA] 6 EN5 [AB] 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 47 2 1 2 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 4 5 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 † This symbol is in accordance with ANSI
PAGE 150
SN74ALVCH16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES015F – JULY 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 151
SN74ALVCH16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES015F – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 152
SN74ALVCH16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES015F – JULY 1995 – REVISED FEBRUARY 1999 operating characteristics, TA = 25° C PARAMETER Outputs enabled Power dissipation capacitance Cpd VCC = 1.8 V TYP † TEST CONDITIONS CL = 50 pF, Outputs disabled f = 10 MHz VCC = 2.5 V TYP VCC = 3.3 V TYP 22 29 4 5 † UNIT pF † This information was not available at the time of publication. PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 153
SN74ALVCH16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES015F – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 154
SN74ALVCH16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES015F – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 2.
PAGE 155
SN74ALVCH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCES046E – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldow
PAGE 156
SN74ALVCH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCES046E – JULY 1995 – REVISED FEBRUARY 1999 Function Tables B TO A (OEB = H) INPUTS 1B 2B SEL LE1B LE2B OEA OUTPUT A H X H H X L H L X H H X L L X X H L X L X H L X H L A0 H X L L X H L L X X L X L L X X X X X H A0 Z A TO B (OEA = H) INPUTS 3–36 LEA2B OUTPUTS A LEA1B OE1B OE2B 1B 2B H H H L H H L L H H L L L H H L L L L H 2B0 2B0 L H L L L
PAGE 157
SN74ALVCH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCES046E – JULY 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) LE1B LE2B LEA1B LEA2B OE2B OE1B OEA SEL A1 2 27 30 55 56 29 1 28 G1 C1 1 1D 8 23 1B1 1 C1 1D 6 2B1 C1 1D C1 1D To 11 Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3–37
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SN74ALVCH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCES046E – JULY 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
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SN74ALVCH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCES046E – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
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SN74ALVCH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCES046E – JULY 1995 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) PARAMETER FROM (INPUT) TO (OUTPUT) A or B tpd ten VCC = 1.8 V VCC = 2.5 V ± 0.2 V MIN MAX B or A TYP † 1 VCC = 2.7 V MIN VCC = 3.3 V ± 0.3 V MAX MIN MAX 5.4 5.1 1.2 4.3 UNIT LE A or B † 1 5.6 5.2 1 4.4 SEL A † 1 6.9 6.6 1.
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SN74ALVCH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCES046E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 162
SN74ALVCH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCES046E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 163
SN74ALVCH16260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCES046E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
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SN74ALVCH16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES019H – JULY 1995 – REVISED FEBRUARY1999 D Member of the Texas Instruments D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown
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SN74ALVCH16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES019H – JULY 1995 – REVISED FEBRUARY1999 Function Tables OUTPUT ENABLE OUTPUTS INPUTS CLK OEA OEB A 1B, 2B ↑ H H Z Z ↑ H L Z Active ↑ L H Active Z ↑ L L Active Active A-TO-B STORAGE (OEB = L) INPUTS OUTPUTS CLKENA1 CLKENA2 CLK A 1B 1B0† 2B 2B0† H H X X L X ↑ L X ↑ L L X H H X X L ↑ L X X L ↑ H L H X † Output level before the indicated steady-state input conditions wer
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SN74ALVCH16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES019H – JULY 1995 – REVISED FEBRUARY1999 logic diagram (positive logic) CLK OEB1 29 C1 2 1D C1 OEB2 CLKENA1 CLKENA2 56 1D 30 55 C1 SEL OEA 28 1D 1 1D 1 of 12 Channels C1 G1 A1 8 C1 1 1D 23 1B1 1 CE C1 1D 6 2B1 CE C1 1D POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3–47
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SN74ALVCH16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES019H – JULY 1995 – REVISED FEBRUARY1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 168
SN74ALVCH16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES019H – JULY 1995 – REVISED FEBRUARY1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 169
SN74ALVCH16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES019H – JULY 1995 – REVISED FEBRUARY1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw Clock frequency MAX † VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN 135 MAX VCC = 3.3 V ± 0.3 V MIN 135 135 † 3.3 3.3 3.3 A data before CLK↑ † 2 2 1.7 B data before CLK↑ † 2.2 2.1 1.8 SEL before CLK↑ † 1.6 1.
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SN74ALVCH16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES019H – JULY 1995 – REVISED FEBRUARY1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 171
SN74ALVCH16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES019H – JULY 1995 – REVISED FEBRUARY1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 172
SN74ALVCH16269 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES019H – JULY 1995 – REVISED FEBRUARY1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 1.5 V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0V tPLH Output Control (low-level enabling) 1.
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SN74ALVCH16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES028F – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options In
PAGE 174
SN74ALVCH16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES028F – JULY 1995 – REVISED FEBRUARY 1999 Function Tables OUTPUT ENABLE INPUTS OUTPUTS CLK OEA OEB A ↑ H H Z 1B, 2B Z ↑ H L Z Active ↑ L H Active Z ↑ L L Active Active A-TO-B STORAGE (OEB = L) INPUTS OUTPUTS CLKENA1 CLKENA2 CLK A 1B 2B L H X X L H X X 1B0† 1B0† 2B0† 2B0† L L ↑ L L L ↑ H L‡ H‡ H H L ↑ L H L ↑ H 1B0† 1B0† H L L H H X X 1B0† 2B0† † Output level befo
PAGE 175
SN74ALVCH16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES028F – JULY 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) 29 CLK 2 CLKEN1B 27 CLKEN2B CLKENA1 30 55 C1 CLKENA2 56 1D OEB 28 SEL 1 OEA CE 1D C1 1D C1 G1 A1 1 1B1 CE C1 1 8 23 1D 1D 6 2B1 CE CE C1 C1 1D 1D CE C1 1D 1 of 12 Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3–57
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SN74ALVCH16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES028F – JULY 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 177
SN74ALVCH16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES028F – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
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SN74ALVCH16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES028F – JULY 1995 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw tsu th Clock frequency Hold time MIN MAX VCC = 2.7 V MIN 150 MAX VCC = 3.3 V ± 0.3 V MIN 150 3.3 3.3 3.3 A data before CLK↑ † 4.1 3.8 3.1 B data before CLK↑ † 0.9 1.2 0.9 CLKENA1 or CLKENA2 before CLK↑ † 3.
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SN74ALVCH16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES028F – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 180
SN74ALVCH16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES028F – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 181
SN74ALVCH16270 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES028F – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 1.5 V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0V tPLH Output Control (low-level enabling) 1.
PAGE 182
SN74ALVCH16271 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES017E – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown
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SN74ALVCH16271 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES017E – JULY 1995 – REVISED FEBRUARY 1999 Function Tables OUTPUT ENABLE INPUTS OUTPUTS OEA OEB A H H Z 1B, 2B Z H L Z Active L H Active Z L L Active Active A-TO-B STORAGE (OEB = L) INPUTS OUTPUTS CLKENA1 CLKENA2 CLK A 1B 2B H H X X L X ↑ L 1B0† L 2B0† X L X ↑ H H X X L ↑ L X L X L ↑ H A0 H B-TO-A STORAGE (OEA = L) INPUTS OUTPUT A LE SEL 1B 2B H X X X H X X
PAGE 184
SN74ALVCH16271 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES017E – JULY 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) CLK 29 2 LE1B 27 LE2B CLKENA1 30 55 CLKENA2 56 OEB 28 SEL LE 23 1 1B1 1D OEA G1 1 8 A1 LE 6 1 1D 2B1 CE C1 1D CE C1 1D 1 of 12 Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3–67
PAGE 185
SN74ALVCH16271 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES017E – JULY 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 186
SN74ALVCH16271 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES017E – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 187
SN74ALVCH16271 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES017E – JULY 1995 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER TO (OUTPUT) fmax CLK VCC = 1.8 V MIN † B B tpd A LE SEL ten OEB or OEA B or A tdis B or A OEB or OEA † This information was not available at the time of publication. TYP VCC = 2.5 V ± 0.2 V MIN MAX 130 VCC = 2.
PAGE 188
SN74ALVCH16271 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES017E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 189
SN74ALVCH16271 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES017E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 190
SN74ALVCH16271 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES017E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 191
SN74ALVCH16272 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES057C – OCTOBER 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Packaged in Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages OEA LE1B 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 G
PAGE 192
SN74ALVCH16272 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES057C – OCTOBER 1995 – REVISED FEBRUARY 1999 Function Tables OUTPUT ENABLE OUTPUTS INPUTS OEA OEB A 1B, 2B H H Z Z H L Z Active L H Active Z L L Active Active A-TO-B STORAGE (OEB = L) OUTPUTS PRODUCT PREVIEW INPUTS CLKENA1 CLKENA2 CLK A 1B 2B H H X X L X ↑ L 1B0† L‡ 2B0† X L X ↑ H H‡ X X L ↑ L X L X L ↑ H A0 H † Output level before the indicated steady-state input conditions
PAGE 193
SN74ALVCH16272 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES057C – OCTOBER 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) LE1B LE2B CLKENA1 CLKENA2 OEB 29 2 27 30 55 LE 56 1D SEL OEA 23 1B1 28 1 G1 LE A1 1 8 6 1D 1 CE 2B1 CE C1 C1 1D 1D CE CE C1 C1 1D 1D To 11 Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3–77 PRODUCT PREVIEW CLK
PAGE 194
SN74ALVCH16272 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES057C – OCTOBER 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 195
SN74ALVCH16272 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES057C – OCTOBER 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 196
SN74ALVCH16272 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES057C – OCTOBER 1995 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER TO (OUTPUT) VCC = 1.8 V MIN TYP VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.
PAGE 197
SN74ALVCH16272 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES057C – OCTOBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 198
SN74ALVCH16272 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES057C – OCTOBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 199
SN74ALVCH16272 12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES057C – OCTOBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 200
SN74ALVCH16280 16-BIT TO 32-BIT REGISTERED BUS EXCHANGER WITH BYTE MASKS AND 3-STATE OUTPUTS SCES033A – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Packaged in Thin Shrink Small-Outline Package VCC GND 2B7 1B7 2B6 GND 1B6 2B5 1B5 VCC 2B4 1B4 2B3 1B3 GND 2B2 1B2 2B1 1B1 VCC GND 2D2 1D2 2D1 1D1 VCC C1 C2 A1 GND A2 A3
PAGE 201
SN74ALVCH16280 16-BIT TO 32-BIT REGISTERED BUS EXCHANGER WITH BYTE MASKS AND 3-STATE OUTPUTS SCES033A – JULY 1995 – REVISED FEBRUARY 1999 Function Tables OUTPUT ENABLE OUTPUTS INPUTS CLK OE DIR A 1B, 2B 1D, 2D ↑ H X Z Z Z ↑ L H Z Active Active ↑ L L Active Z Active A-TO-B STORAGE (OE = L, DIR = H) INPUTS OUTPUTS SEL CLK A H X X L ↑ L 1B 1B0† 2B 2B0† L‡ H‡ L PRODUCT PREVIEW L ↑ H H † Output level before the indicated steady-state input conditions were established ‡ T
PAGE 202
SN74ALVCH16280 16-BIT TO 32-BIT REGISTERED BUS EXCHANGER WITH BYTE MASKS AND 3-STATE OUTPUTS SCES033A – JULY 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) 39 CLK 40 SEL 42 OE CE 41 DIR C1 1D 1D 1B1 G1 C1 CE 1 29 1D A1 1 C1 1D 1D 18 2B1 CE C1 C1 1D 1D CE C1 1D 1 of 16 Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3–87 PRODUCT PREVIEW 19
PAGE 203
SN74ALVCH16280 16-BIT TO 32-BIT REGISTERED BUS EXCHANGER WITH BYTE MASKS AND 3-STATE OUTPUTS SCES033A – JULY 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) (mask bits) 39 CLK 40 SEL 42 OE C1 C1 27 CE C1 1D 25 1D 1D 1D1 CE C1 24 PRODUCT PREVIEW 1D C1 C2 CE 28 C1 1D 2D1 1D 23 1D2 CE C1 1D 3–88 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 22 2D2
PAGE 204
SN74ALVCH16280 16-BIT TO 32-BIT REGISTERED BUS EXCHANGER WITH BYTE MASKS AND 3-STATE OUTPUTS SCES033A – JULY 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
PAGE 205
SN74ALVCH16280 16-BIT TO 32-BIT REGISTERED BUS EXCHANGER WITH BYTE MASKS AND 3-STATE OUTPUTS SCES033A – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA PRODUCT PREVIEW UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.
PAGE 206
SN74ALVCH16280 16-BIT TO 32-BIT REGISTERED BUS EXCHANGER WITH BYTE MASKS AND 3-STATE OUTPUTS SCES033A – JULY 1995 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw MAX VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.
PAGE 207
SN74ALVCH16280 16-BIT TO 32-BIT REGISTERED BUS EXCHANGER WITH BYTE MASKS AND 3-STATE OUTPUTS SCES033A – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
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SN74ALVCH16280 16-BIT TO 32-BIT REGISTERED BUS EXCHANGER WITH BYTE MASKS AND 3-STATE OUTPUTS SCES033A – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
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SN74ALVCH16280 16-BIT TO 32-BIT REGISTERED BUS EXCHANGER WITH BYTE MASKS AND 3-STATE OUTPUTS SCES033A – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 0V 1.5 V 0V tsu PRODUCT PREVIEW 1.5 V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
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SN74ALVCH16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES036C – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D DBB PACKAGE (TOP VIEW) Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resis
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SN74ALVCH16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES036C – JULY 1995 – REVISED FEBRUARY 1999 Function Tables A-TO-B STORAGE (OE = L, DIR = H) OUTPUTS INPUTS SEL CLK A H X X L ↑ L 1B 1B0† 2B 2B0† L‡ H‡ X L ↑ H X † Output level before indicated steady-state input conditions were established ‡ Two CLK edges are needed to propagate the data.
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SN74ALVCH16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES036C – JULY 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) CLK SEL OE 39 40 42 CE C1 DIR 41 1D 25 1 of 18 Channels 1B1 G1 CE C1 A1 27 C1 1 1D 1D 1 24 2B1 CE C1 C1 1D 1D CE C1 1D POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3–97
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SN74ALVCH16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES036C – JULY 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
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SN74ALVCH16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES036C – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
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SN74ALVCH16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES036C – JULY 1995 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw tsu th Clock frequency Hold time MIN MAX VCC = 2.7 V MIN 150 MAX VCC = 3.3 V ± 0.3 V MIN 150 3.3 3.3 3.3 A data before CLK↑ † 2.4 2.3 2 B data before CLK↑ † 2.2 2.2 1.8 DIR before CLK↑ † 2.2 2.1 1.
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SN74ALVCH16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES036C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
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SN74ALVCH16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES036C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 218
SN74ALVCH16282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES036C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
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SN74ALVC16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES128C – FEBRUARY 1998 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Ideal for Use in PC100 Register DIMM Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) La
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SN74ALVC16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES128C – FEBRUARY 1998 – REVISED FEBRUARY 1999 FUNCTION TABLE INPUTS CLK A OUTPUT Y X X X Z L X L L L L X H H L H ↑ L L L H ↑ H H Y0† OE LE H L L H L or H X † Output level before the indicated steady-state input conditions were established logic symbol‡ OE CLK LE 1 EN1 48 25 2C3 C3 G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 2 3 1 1 3D 46 5 44 6 43 1 8 41 9 40 11 38 12 37 13
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SN74ALVC16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES128C – FEBRUARY 1998 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1 OE 48 CLK LE 25 47 A1 1D C1 2 Y1 CLK To 15 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . .
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SN74ALVC16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES128C – FEBRUARY 1998 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
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SN74ALVC16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES128C – FEBRUARY 1998 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA VO = VCC or GND VI = VCC or GND, Ci One input at VCC – 0.6 V, Control inputs Data inputs IO = 0 Other inputs at VCC or GND UNIT VCC–0.2 1.2 2.
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SN74ALVC16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES128C – FEBRUARY 1998 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER TO (OUTPUT) fmax VCC = 1.8 V MIN † A tpd Y LE CLK ten tdis VCC = 2.5 V ± 0.2 V TYP MIN VCC = 2.7 V MAX 150 MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz † 1 3.7 3.6 1.1 3.3 † 1 4.8 5 1.3 4.4 † 1 4.
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SN74ALVC16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES128C – FEBRUARY 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
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SN74ALVC16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES128C – FEBRUARY 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 227
SN74ALVC16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES128C – FEBRUARY 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
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SN74ALVCH16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES090H – OCTOBER 1996 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per
PAGE 229
SN74ALVCH16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES090H – OCTOBER 1996 – REVISED FEBRUARY 1999 FUNCTION TABLE INPUTS CLK A OUTPUT Y X X X Z L X L L L L X H H L H ↑ L L L H ↑ H H Y0† OE LE H L L H L or H X † Output level before the indicated steady-state input conditions were established logic symbol‡ OE CLK LE 1 EN1 48 25 2C3 C3 G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 2 1 1 3D 3 46 5 44 6 43 1 8 41 9 40 11 38 12 37 13
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SN74ALVCH16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES090H – OCTOBER 1996 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1 OE 48 CLK LE 25 47 A1 1D C1 2 Y1 CLK To 15 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . .
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SN74ALVCH16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES090H – OCTOBER 1996 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
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SN74ALVCH16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES090H – OCTOBER 1996 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
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SN74ALVCH16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES090H – OCTOBER 1996 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw tsu Clock frequency Pulse duration Setup time MIN MAX MIN 150 MAX VCC = 3.3 V ± 0.3 V MIN 150 3.3 3.3 3.3 CLK high or low † 3.3 3.3 3.3 Data before CLK↑ † 1.4 1.7 1.5 CLK high † 1.2 1.6 1.3 CLK low † 1.4 1.5 1.
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SN74ALVCH16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES090H – OCTOBER 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 235
SN74ALVCH16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES090H – OCTOBER 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 236
SN74ALVCH16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES090H – OCTOBER 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 237
SN74ALVCH16344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES054F – SEPTEMBER 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and T
PAGE 238
SN74ALVCH16344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES054F – SEPTEMBER 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) OE4 56 29 OE3 OE2 OE1 28 1 2 3 1A 34 1B1 5B1 33 1B2 8 5A 5 6 9 31 5B3 1B3 30 1B4 41 2B1 10 2A 6A 12 13 16 17 6B1 6B2 42 38 2B3 37 2B4 48 3B1 47 3B2 15 6B3 6B4 7B1 7B2 43 3A 7A 19 20 23 24 21 45 3B3 44 3B4 55 4B1 54 4B2 4A 49 7B3 7B4 8B1 8B2 8A 26 27 3–126 5B4 40 2B2 14 5B2 36 52 4B3 51 4B4 POS
PAGE 239
SN74ALVCH16344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES054F – SEPTEMBER 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
PAGE 240
SN74ALVCH16344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES054F – SEPTEMBER 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
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SN74ALVCH16344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES054F – SEPTEMBER 1995 – REVISED FEBRUARY 1999 operating characteristics, TA = 25°C PARAMETER Outputs enabled Power dissipation capacitance Cpd VCC = 1.8 V TYP † TEST CONDITIONS CL = 50 pF, Outputs disabled f = 10 MHz VCC = 2.5 V TYP † VCC = 3.3 V TYP 68 84 11 14 UNIT pF † This information was not available at the time of publication. PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 242
SN74ALVCH16344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES054F – SEPTEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 243
SN74ALVCH16344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES054F – SEPTEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 244
SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES020C – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-833, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistor
PAGE 245
SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES020C – JULY 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE (each 8-bit section) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic symbol† 1OE 1LE 2OE 2LE 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 1 1EN 48 C3 24 2EN 25 C4 47 3D 2 1 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 4D 2 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1Q1 1Q2 1Q3 1Q4 1Q5 1
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SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES020C – JULY 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
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SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES020C – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
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SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES020C – JULY 1995 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) PARAMETER FROM (INPUT) D tpd MIN MAX 1 † Q OE VCC = 2.5 V ± 0.2 V TYP † Q LE ten VCC = 1.8 V TO (OUTPUT) tdis Q OE † This information was not available at the time of publication. VCC = 2.7 V MIN VCC = 3.3 V ± 0.3 V UNIT MAX MIN MAX 4.5 4.
PAGE 249
SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES020C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 250
SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES020C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 251
SN74ALVCH16373 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS SCES020C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 252
SN74ALVCH16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES021D – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 GND 1Q7 1Q8 2Q1 2Q2 GND 2Q3 2Q4 VCC 2Q5 2Q6 GND 2Q7 2Q8 2OE D Latch-Up Performance Exceeds
PAGE 253
SN74ALVCH16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES021D – JULY 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z logic symbol† 1OE 1CLK 2OE 2CLK 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 1 1EN 48 C1 24 2EN 25 C2 47 1D 2 1 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 2D 2 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1Q1 1Q2 1Q
PAGE 254
SN74ALVCH16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES021D – JULY 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
PAGE 255
SN74ALVCH16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES021D – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 256
SN74ALVCH16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES021D – JULY 1995 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER fmax tpd CLK ten OE VCC = 1.8 V TO (OUTPUT) MIN † TYP VCC = 2.5 V ± 0.2 V MIN MAX 150 VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz Q † 1 5.3 4.9 1 4.2 ns Q † 1 6.2 5.9 1 4.
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SN74ALVCH16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES021D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
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SN74ALVCH16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES021D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 259
SN74ALVCH16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES021D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V 500 Ω From Output Under Test Open S1 GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 2.7 V 1.
PAGE 260
SN74ALVCH16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES022E – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus+ Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process UBE  (Universal Bus Exchanger) Allows Synchronous Data Exchange ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold
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SN74ALVCH16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES022E – JULY 1995 – REVISED FEBRUARY 1999 Function Tables INPUTS CLK SEND PORT X X OUTPUT RECEIVE PORT X L B0† L X H H ↑ L L ↑ H H X H B0† B0† † Output level before the indicated steady-state input conditions were established L X DATA-FLOW CONTROL INPUTS PRE 3–150 SEL1 SEL2 CLK SEL0 H X X X X X X X L H ↑ X X X X X No change L L ↑ 0 0 0 0 0 None, all I/Os off L L ↑ 0 0 0 0
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SN74ALVCH16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES022E – JULY 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) CLK SELEN 1 56 PRE 55 28 SEL2 2 29 SEL0 SEL1 SEL3 Flow and Storage Control 30 27 SEL4 3 3 2Ax 1Ax CLK D 1A 1Ax CLK D 2A CLK D 1Bx 2Ax 2Bx 2Bx 3 1B 1Bx 3 1Ax 1Ax 1Bx 2Bx 2Ax 1Bx CLK D 2Ax 2B 2Bx One of Nine Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VC
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SN74ALVCH16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES022E – JULY 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 264
SN74ALVCH16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES022E – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
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SN74ALVCH16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES022E – JULY 1995 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw tsu th Clock frequency Hold time MIN MAX VCC = 2.7 V MIN 120 MAX VCC = 3.3 V ± 0.3 V MIN 120 4.2 4.2 3 A or B before CLK↑ † 1.9 1.9 1.4 SEL before CLK↑ † 5.1 4.2 3.5 SELEN before CLK↑ † 2.5 2.5 1.
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SN74ALVCH16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES022E – JULY 1995 – REVISED FEBRUARY 1999 timing diagram CLK tsu th tsu th SELEN SEL (0-4) ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tsu Selected Input Port Selected Output Port ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ th ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tpd CLK to Output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3–155
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SN74ALVCH16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES022E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 268
SN74ALVCH16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES022E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 269
SN74ALVCH16409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES022E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 1.5 V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V Output Control (low-level enabling) 2.7 V 1.5 V 1.5 V 0V tPZL 2.7 V 1.
PAGE 270
SN74ALVCH16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES023F – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process UBT  (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 p
PAGE 271
SN74ALVCH16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES023F – JULY 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE† INPUTS OEAB LEAB CLKAB A OUTPUT B Z L X X X H H X L L H H X H H H L O L L H L ↓ H H B0‡ H L L or H X † A-to-B data flow is shown: B-to-A flow is similar, but uses OEBA, LEBA, and CLKBA.
PAGE 272
SN74ALVCH16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES023F – JULY 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1 OEAB 55 CLKAB 2 LEAB 28 LEBA 30 CLKBA 27 OEBA 3 A1 1D C1 CLK 54 B1 1D C1 CLK To 17 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 273
SN74ALVCH16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES023F – JULY 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 274
SN74ALVCH16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES023F – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 275
SN74ALVCH16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES023F – JULY 1995 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock Clock frequency MAX † VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN 150 MAX VCC = 3.3 V ± 0.3 V MIN 150 150 LE high † 3.3 3.3 3.3 CLK high or low † 3.3 3.3 3.3 Data before CLK↓ † 1.7 1.4 1.3 CLK high † 1.
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SN74ALVCH16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES023F – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 277
SN74ALVCH16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES023F – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 278
SN74ALVCH16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES023F – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 279
SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES024C – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process UBT  (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 p
PAGE 280
SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES024C – JULY 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE† INPUTS OEAB LEAB CLKAB A OUTPUT B Z L X X X H H X L L H H X H H H L ↑ L L H L ↑ H H B0‡ H L L or H X † A-to-B data flow is shown: B-to-A flow is similar, but uses OEBA, LEBA, and CLKBA.
PAGE 281
SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES024C – JULY 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) OEAB CLKAB LEAB LEBA CLKBA OEBA A1 1 55 2 28 30 27 3 1D C1 CLK 54 B1 1D C1 CLK To 17 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 282
SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES024C – JULY 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 283
SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES024C – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 284
SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES024C – JULY 1995 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) PARAMETER FROM (INPUT) VCC = 1.8 V TO (OUTPUT) MIN † fmax A or B tpd LE CLK ten tdis ten tdis B or A A or B TYP VCC = 2.5 V ± 0.2 V MIN MAX 150 VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz † 1 4.8 4.5 1 3.9 † 1.1 5.
PAGE 285
SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES024C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 286
SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES024C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 287
SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES024C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 288
SN74ALVCH16524 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES080C – JULY 1996 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D Widebus Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Pla
PAGE 289
SN74ALVCH16524 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES080C – JULY 1996 – REVISED FEBRUARY 1999 FUNCTION TABLE B-TO-A STORAGE (OEBA = L) INPUTS CLKENBA CLK SEL B H X X X L ↑ H L L ↑ H H L ↑ L L OUTPUT A A0† L H L‡ H‡ L ↑ L H † Output level before the indicated steady-state input conditions were established ‡ Four positive CLK edges are needed to propagate data from B to A when SEL is low.
PAGE 290
SN74ALVCH16524 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES080C – JULY 1996 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 291
SN74ALVCH16524 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES080C – JULY 1996 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 292
SN74ALVCH16524 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES080C – JULY 1996 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER VCC = 1.8 V TO (OUTPUT) MIN † fmax MIN MAX 120 VCC = 2.7 V MIN MAX 125 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz A B † 1 3.9 3.8 1 3.2 CLK A † 1 6.1 6.2 1 5.2 OEAB or OEBA A or B † 1 6.1 6.1 1 5.
PAGE 293
SN74ALVCH16524 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES080C – JULY 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 294
SN74ALVCH16524 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES080C – JULY 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 295
SN74ALVCH16524 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES080C – JULY 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 296
SN74ALVCH16525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES059C – NOVEMBER 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Option Include
PAGE 297
SN74ALVCH16525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES059C – NOVEMBER 1995 – REVISED FEBRUARY 1999 Function Tables A-TO-B STORAGE (OEAB = L) INPUTS CLKENAB CLKAB A H X X L ↑ L L ↑ H OUTPUT B B0† L H † Output level before the indicated steady-state input conditions were established B-TO-A STORAGE (OEBA = L) INPUTS CLKENBA CLK2BA CLK1BA SEL B H X X X X L ↑ X H L L ↑ X H H L ↑ ↑ L L OUTPUT A A0† L H L‡ H‡ L ↑ ↑ L H † Output level before the indicated
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SN74ALVCH16525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES059C – NOVEMBER 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) CLKAB CLK1BA CLK2BA CLKENBA CLKENAB OEAB OEBA SEL 55 30 29 28 1 2 27 56 1 of 18 Channels G1 CE 3 A1 C1 1D CE 1 1 C1 1D CE C1 1D CE C1 1D 54 B1 CE C1 1D POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3–189
PAGE 299
SN74ALVCH16525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES059C – NOVEMBER 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 300
SN74ALVCH16525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES059C – NOVEMBER 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 301
SN74ALVCH16525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES059C – NOVEMBER 1995 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw Clock frequency Setup time th Hold time MIN VCC = 2.7 V MAX MIN 120 MAX VCC = 3.3 V ± 0.3 V MIN 125 3.2 3.2 3 A data before CLKAB↑ † 1.3 1.3 1.3 B data before CLK2BA↑ † 2.1 1.8 1.7 B data before CLK1BA↑ † 1.3 1.
PAGE 302
SN74ALVCH16525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES059C – NOVEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 303
SN74ALVCH16525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES059C – NOVEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 304
SN74ALVCH16525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES059C – NOVEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 305
SN74ALVCH16540 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES029B – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages 1OE1 1Y1 1Y2 GND 1Y3 1Y4 VCC 1Y5 1Y6 GND 1Y7 1Y8 2Y1 2Y2 GND 2Y3 2Y4 VCC 2Y5 2Y6 GND 2Y7 2Y8 2
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SN74ALVCH16540 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES029B – JULY 1995 – REVISED FEBRUARY 1999 logic symbol† 1OE1 1 & 48 EN1 1OE2 2OE1 2OE2 1A1 1A2 1A3 1A4 1A5 1A6 1A7 PRODUCT PREVIEW 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 24 & EN2 25 47 1 46 2 1 3 44 5 43 6 41 8 40 9 38 11 37 12 13 36 1 35 2 14 33 16 32 17 30 19 29 20 27 22 26 23 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 2Y1 2Y2 2Y3 2Y4 2Y5 2Y6 2Y7 2Y8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and I
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SN74ALVCH16540 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES029B – JULY 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
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SN74ALVCH16540 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES029B – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA PRODUCT PREVIEW UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
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SN74ALVCH16540 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES029B – JULY 1995 – REVISED FEBRUARY 1999 operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance Outputs enabled Outputs disabled CL = 0, VCC = 1.8 V TYP VCC = 2.5 V TYP VCC = 3.3 V TYP f = 10 MHz UNIT pF PARAMETER MEASUREMENT INFORMATION VCC = 1.
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SN74ALVCH16540 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES029B – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
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SN74ALVCH16540 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES029B – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) 2.7 V 1.
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SN74ALVCH16541 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES031B – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages 1OE1 1Y1 1Y2 GND 1Y3 1Y4 VCC 1Y5 1Y6 GND 1Y7 1Y8 2Y1 2Y2 GND 2Y3 2Y4 VCC 2Y5 2Y6 GND 2Y7 2Y8 2
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SN74ALVCH16541 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES031B – JULY 1995 – REVISED FEBRUARY 1999 logic symbol† 1OE1 1 & EN1 48 1OE2 2OE1 2OE2 1A1 1A2 1A3 1A4 1A5 1A6 1A7 PRODUCT PREVIEW 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 24 & EN2 25 47 1 2 1 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 1 2 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 2Y1 2Y2 2Y3 2Y4 2Y5 2Y6 2Y7 2Y8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and
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SN74ALVCH16541 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES031B – JULY 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
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SN74ALVCH16541 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES031B – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA PRODUCT PREVIEW UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
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SN74ALVCH16541 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES031B – JULY 1995 – REVISED FEBRUARY 1999 operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance Outputs enabled Outputs disabled CL = 0, VCC = 1.8 V TYP VCC = 2.5 V TYP VCC = 3.3 V TYP f = 10 MHz UNIT pF PARAMETER MEASUREMENT INFORMATION VCC = 1.
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SN74ALVCH16541 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES031B – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
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SN74ALVCH16541 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES031B – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) 2.7 V 1.
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SN74ALVCH16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES025D – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plasti
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SN74ALVCH16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES025D – JULY 1995 – REVISED FEBRUARY 1999 logic symbol† 1OEBA 1CEBA 1LEBA 1OEAB 1CEAB 1LEAB 2OEBA 2CEBA 2LEBA 2OEAB 2CEAB 56 54 55 1 G1 1C5 2EN4 3 G2 2 2C6 29 31 30 28 26 27 2LEAB 1A1 1EN3 7EN9 G7 7C11 8EN10 G8 8C12 5 3 6D 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 6 2A3 2A4 2A5 2A6 2A7 2A8 4 51 49 9 48 10 47 12 45 13 44 14 43 15 9 16 11D 10 42 41 17 40 19 38 20 37 21 36 23 34 24 33 † This symbol is in acco
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SN74ALVCH16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES025D – JULY 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1OEBA 1CEBA 1LEBA 1OEAB 1CEAB 1LEAB 1A1 56 54 55 1 3 2 C1 5 1D 52 1B1 C1 1D To Seven Other Channels 2OEBA 2CEBA 2LEBA 2OEAB 2CEAB 2LEAB 2A1 29 31 30 28 26 27 C1 15 1D 42 2B1 C1 1D To Seven Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3–215
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SN74ALVCH16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES025D – JULY 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE† (each 8-bit section) INPUTS CEAB LEAB OEAB A OUTPUT B H X X X Z X X H X Z L H L X L L L L B0‡ L L L L H H † A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA.
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SN74ALVCH16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES025D – JULY 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
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SN74ALVCH16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES025D – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
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SN74ALVCH16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES025D – JULY 1995 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) PARAMETER FROM (INPUT) TO (OUTPUT) A or B tpd ten tdis ten tdis VCC = 1.8 V VCC = 2.5 V ± 0.2 V MIN MAX B or A TYP † 1 LE A or B † CE A or B CE A or B OE OE VCC = 2.7 V MIN VCC = 3.3 V ± 0.3 V UNIT MAX MIN MAX 5.1 4.8 1 4.3 1 6.5 6.2 1.
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SN74ALVCH16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES025D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
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SN74ALVCH16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES025D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
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SN74ALVCH16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES025D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
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SN74ALVCH16600 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES030D – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process UBT  (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine M
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SN74ALVCH16600 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES030D – JULY 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE† INPUTS OUTPUT B CLKENAB OEAB LEAB CLKAB A X H X X X Z X L H X L L X L H X H H H L L X X H L L X X B0‡ B0‡ L L L ↓ L L L L L ↓ H H B0‡ L L L L or H X † A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA.
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SN74ALVCH16600 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES030D – JULY 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
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SN74ALVCH16600 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES030D – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 333
SN74ALVCH16600 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES030D – JULY 1995 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw tsu th Clock frequency Pulse duration MAX MIN 150 MAX VCC = 3.3 V ± 0.3 V MIN 150 LE high 3.3 3.3 3.3 † 3.3 3.3 3.3 Data before CLK↑ † 1.3 1.3 1.2 CLK high † 1.2 1.1 1.1 CLK low † 1.8 1.5 1.
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SN74ALVCH16600 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES030D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 335
SN74ALVCH16600 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES030D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 336
SN74ALVCH16600 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES030D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 337
SN74ALVCH16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES027D – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family UBT  (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine M
PAGE 338
SN74ALVCH16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES027D – JULY 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE† INPUTS A OUTPUT B CLKENAB OEAB LEAB CLKAB X H X X X Z X L H X L L X L H X H H H L L X X H L L X X B0‡ B0‡ L L L ↑ L L L L L ↑ H H B0‡ L L L L or H X † A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA.
PAGE 339
SN74ALVCH16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES027D – JULY 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 340
SN74ALVCH16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES027D – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 341
SN74ALVCH16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES027D – JULY 1995 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock Clock frequency Pulse duration tw tsu Setup time th Hold time MAX † VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN 150 MAX VCC = 3.3 V ± 0.3 V MIN 150 150 LE high † 3.3 3.3 3.3 CLK high or low † 3.3 3.3 3.
PAGE 342
SN74ALVCH16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES027D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 343
SN74ALVCH16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES027D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 344
SN74ALVCH16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES027D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 345
SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES032E– JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include P
PAGE 346
SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES032E– JULY 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE INPUTS DATA I/Os OE DIR CLKAB CLKBA SAB SBA A1–A8 B1–B8 X X ↑ X X X Input Unspecified† OPERATION OR FUNCTION X X X ↑ X X Unspecified† Input Store A, B unspecified† Store B, A unspecified† H X ↑ ↑ X X Input Input Store A and B data H X H or L H or L X X Input disabled Input disabled Isolation, hold storage L L X X X L Output I
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SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS OE L DIR L CLKAB CLKBA X X SAB X BUS B BUS A BUS A BUS B SCES032E– JULY 1995 – REVISED FEBRUARY 1999 SBA L OE L DIR H DIR X X X CLKAB CLKBA X ↑ X ↑ ↑ ↑ SAB L SAB X X X SBA X BUS B BUS A BUS A OE X X H CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A CLKAB X SBA X X X OE L L DIR L H CLKAB X H or L CLKBA H or L X SAB X H SBA H X TRANSFER STORED DATA TO A AND/OR B STORAGE F
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SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES032E– JULY 1995 – REVISED FEBRUARY 1999 logic symbol† 1OE 1DIR 1CLKBA 1SBA 1CLKAB 1SAB 2OE 2DIR 2CLKBA 2SBA 2CLKAB 2SAB 1A1 56 1 55 54 2 G3 3 EN1 [BA] 3 EN2 [AB] C4 G5 C6 3 G7 29 28 30 31 27 26 G10 10 EN8 [BA] 10 EN9 [AB] C11 G12 C13 G14 ≥1 5 1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 7 1 2A3 2A4 2A5 2A6 2A7 2A8 ≥1 7 51 49 9 48 10 47 12 45 13 44 14 43 15 16 ≥1 8 1 14 12 11D 42 ≥1 1B3 1B4 1B5 1B6 1B7 1B8 2B1
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SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES032E– JULY 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) 56 1OE 1DIR 1CLKBA 1SBA 1CLKAB 1SAB 1 55 54 2 3 One of Eight Channels 1D C1 1A1 5 52 1B1 1D C1 2OE To Seven Other Channels 29 28 2DIR 2CLKBA 2SBA 2CLKAB 2SAB 30 31 27 26 One of Eight Channels 1D C1 2A1 15 42 2B1 1D C1 To Seven Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3–243
PAGE 350
SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES032E– JULY 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 351
SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES032E– JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 352
SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES032E– JULY 1995 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 4) PARAMETER FROM (INPUT) VCC = 1.8 V TO (OUTPUT) MIN † fmax A or B tpd B or A CLKAB or CLKBA SAB or SBA A or B TYP VCC = 2.5 V ± 0.2 V MIN MAX 150 VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz † 1 4.8 4.5 1 3.9 † 1 5.
PAGE 353
SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES032E– JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 354
SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES032E– JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 355
SN74ALVCH16646 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES032E– JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 356
SN74ALVCH16652 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES034A – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D description This 16-bit bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH16652 consists of D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers.
PAGE 357
SN74ALVCH16652 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES034A – JULY 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE DATA I/O† INPUTS OEAB OEBA CLKAB CLKBA SAB SBA L H H or L H or L X L H ↑ ↑ X X H ↑ H or L H H ↑ ↑ X X‡ L X H or L ↑ X L L ↑ ↑ X X X‡ L L X X X L L L X H or L X H H H X X L H H H or L X H H L H or L H or L H H OPERATION OR FUNCTION A1–A8 B1–B8 X Input Input Isolation X Input Input Store A and B data X
PAGE 358
SN74ALVCH16652 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS L L CLKAB CLKBA SAB X X X SBA L BUS B OEAB OEBA H H X L L H X H ↑ X ↑ CLKBA SAB X ↑ ↑ SAB L X X X SBA X BUS B BUS A BUS A OEAB OEBA CLKAB CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A CLKAB X PRODUCT PREVIEW OEAB OEBA BUS A BUS A BUS B SCES034A – JULY 1995 – REVISED FEBRUARY 1999 SBA X X X STORAGE FROM A, B, OR A AND B OEAB OEBA H L CLKAB CLKBA SAB SBA H or L H o
PAGE 359
SN74ALVCH16652 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES034A – JULY 1995 – REVISED FEBRUARY 1999 logic symbol† 1OEBA 1OEAB 1CLKBA 1SBA 1CLKAB 1SAB 2OEBA 2OEAB 2CLKBA 2SBA 2CLKAB 2SAB 1A1 56 1 55 54 2 EN1 [BA] EN2 [AB] C3 G4 C5 3 29 28 30 31 27 26 G6 EN7 [BA] EN8 [AB] C9 G10 C11 G12 ≥1 5 3D 4 1 52 1B1 PRODUCT PREVIEW 4 1 5D 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 6 1 6 ≥1 2 6 51 8 49 9 48 10 47 12 45 13 44 14 43 ≥1 15 10 7 9D 42 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2
PAGE 360
SN74ALVCH16652 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES034A – JULY 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) 56 1OEBA 1OEAB 1CLKBA 1SBA 1CLKAB 1SAB 1 55 54 2 3 One of Eight Channels 1D C1 1A1 5 52 1B1 PRODUCT PREVIEW 1D C1 To Seven Other Channels 29 2OEBA 2OEAB 2CLKBA 2SBA 2CLKAB 2SAB 28 30 31 27 26 One of Eight Channels 1D C1 2A1 15 42 2B1 1D C1 To Seven Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3–255
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SN74ALVCH16652 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES034A – JULY 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 362
SN74ALVCH16652 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES034A – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 363
SN74ALVCH16652 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES034A – JULY 1995 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 4) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V MIN TYP VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.
PAGE 364
SN74ALVCH16652 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES034A – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 365
SN74ALVCH16652 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES034A – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 366
SN74ALVCH16652 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS SCES034A – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 367
SN74ALVCH16721 3.
PAGE 368
SN74ALVCH16721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCES052D – JULY 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE (each flip-flop) INPUTS OE CLKEN CLK D OUTPUT Q L H X X Q0 L L ↑ H H L L ↑ L L L L L or H X Q0 H X X X Z logic diagram (positive logic) 1 OE 56 CLK 29 CE CLKEN C1 D1 55 1D 2 Q1 To 19 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . .
PAGE 369
SN74ALVCH16721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCES052D – JULY 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 370
SN74ALVCH16721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCES052D – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 371
SN74ALVCH16721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCES052D – JULY 1995 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) PARAMETER FROM (INPUT) fmax tpd CLK ten OE VCC = 1.8 V TO (OUTPUT) MIN † TYP VCC = 2.5 V ± 0.2 V MIN MAX 150 VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz Q † 1 5.6 1 5.1 1 4.3 ns Q † 1 6.1 1 5.8 1 4.8 ns † 1 5.
PAGE 372
SN74ALVCH16721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCES052D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 373
SN74ALVCH16721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCES052D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 374
SN74ALVCH16721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCES052D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 375
SN74ALVCH16820 3.
PAGE 376
SN74ALVCH16820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS SCES035E – JULY 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE (each flip-flop) INPUTS OEn† L CLK D OUTPUT Qn† ↑ H H L ↑ L L L L X Q0 H † n = 1, 2 X X Z logic diagram (positive logic) 1 1OE 28 2OE 2 56 CLK C1 D1 55 1Q1 3 1Q2 1D To Nine Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . .
PAGE 377
SN74ALVCH16820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS SCES035E – JULY 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 378
SN74ALVCH16820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS SCES035E – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 379
SN74ALVCH16820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS SCES035E – JULY 1995 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER fmax tpd CLK ten OE VCC = 1.8 V TO (OUTPUT) MIN † MAX VCC = 2.5 V ± 0.2 V MIN MAX 150 VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz Q † 1 5.9 5.5 1 4.8 ns Q † 1 6.4 6.
PAGE 380
SN74ALVCH16820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS SCES035E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 381
SN74ALVCH16820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS SCES035E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 382
SN74ALVCH16820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS SCES035E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 383
SN74ALVCH16821 3.
PAGE 384
SN74ALVCH16821 3.
PAGE 385
SN74ALVCH16821 3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCES037C – JULY 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1 1OE 56 1CLK One of Ten Channels C1 55 1D1 2 1D 1Q1 To Nine Other Channels 28 2OE 29 2CLK One of Ten Channels C1 42 2D1 1D 15 2Q1 To Nine Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 386
SN74ALVCH16821 3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCES037C – JULY 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 387
SN74ALVCH16821 3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCES037C – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 388
SN74ALVCH16821 3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCES037C – JULY 1995 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) PARAMETER FROM (INPUT) fmax tpd ten tdis VCC = 1.8 V TO (OUTPUT) MIN † TYP VCC = 2.5 V ± 0.2 V MIN MAX 150 VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz CLK Q † 1 5.8 5.3 1 4.5 ns OE Q † 1 6.6 6.2 1 5.
PAGE 389
SN74ALVCH16821 3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCES037C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 390
SN74ALVCH16821 3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCES037C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 391
SN74ALVCH16821 3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCES037C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 392
SN74ALVCH16823 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCES038D – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
PAGE 393
SN74ALVCH16823 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCES038D – JULY 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE (each 9-bit flip-flop) INPUTS OE CLR CLKEN CLK D OUTPUT Q L L X X X L L H L ↑ H H L H L ↑ L L L H L L X Q0 L H H X X Q0 H X X X X Z logic symbol† 1OE 1CLR 2 EN1 1 R2 55 1CLKEN 1CLK 2OE 2CLR 2CLKEN 2CLK 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 56 27 28 30 29 54 G3 3C4 EN5 R6 G7 7C8 4D 52 1, 2 5 51 6
PAGE 394
SN74ALVCH16823 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCES038D – JULY 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1OE 1CLR 1CLKEN 2 1 55 CE R 1CLK 1D1 56 C1 54 3 1Q1 1D To Eight Other Channels 2OE 2CLR 2CLKEN 27 28 30 CE R 2CLK 2D1 29 C1 42 15 2Q1 1D To Eight Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 395
SN74ALVCH16823 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCES038D – JULY 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 396
SN74ALVCH16823 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCES038D – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 397
SN74ALVCH16823 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCES038D – JULY 1995 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw tsu th Clock frequency Pulse duration Setup time Hold time MAX † VCC = 2.5 V MIN MAX VCC = 2.7 V MIN 150 MAX VCC = 3.3 V ± 0.3 V MIN 150 150 CLR low † 3.3 3.3 3.3 CLK high or low † 3.3 3.3 3.3 CLR inactive † 0.7 0.7 0.
PAGE 398
SN74ALVCH16823 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCES038D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 399
SN74ALVCH16823 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCES038D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 400
SN74ALVCH16823 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCES038D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V S1 500 Ω From Output Under Test 6V Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 401
SN74ALVCH16825 18-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES039C – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Op
PAGE 402
SN74ALVCH16825 18-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES039C – JULY 1995 – REVISED FEBRUARY 1999 logic symbol† 1 & 1OE1 EN1 56 1OE2 2OE1 2OE2 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 2A1 2A2 2A2 2A3 2A4 2A5 2A6 2A7 2A8 28 & 29 EN2 55 2 1 54 3 52 5 51 6 49 8 48 9 47 10 45 12 44 13 41 16 2 40 17 38 19 37 20 36 21 34 23 33 24 31 26 30 27 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 1Y9 2Y1 2Y2 2Y3 2Y4 2Y5 2Y6 2Y7 2Y8 2Y9 † This symbol is in accordance with ANSI/IEEE Std 91-1
PAGE 403
SN74ALVCH16825 18-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES039C – JULY 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 404
SN74ALVCH16825 18-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES039C – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 405
SN74ALVCH16825 18-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES039C – JULY 1995 – REVISED FEBRUARY 1999 operating characteristics, TA = 25°C PARAMETER Outputs enabled Power dissipation capacitance Cpd VCC = 1.8 V TYP † TEST CONDITIONS CL = 50 pF, Outputs disabled f = 10 MHz VCC = 2.5 V TYP VCC = 3.3 V TYP 16 18 4 6 † UNIT pF † This information was not available at the time of publication. PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 406
SN74ALVCH16825 18-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES039C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 407
SN74ALVCH16825 18-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES039C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 408
SN74ALVCH16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES041C – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package O
PAGE 409
SN74ALVCH16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES041C – JULY 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE (each 10-bit section) INPUTS OE1 OE2 A OUTPUT Y L L L L L L H H H X X Z X H X Z logic symbol† 1OE1 1OE2 2OE1 2OE2 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1A10 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 2A10 1 & EN1 56 28 & EN2 29 55 1 1 54 3 52 5 51 6 49 8 48 9 47 10 45 12 44 13 43 14 42 15 1 2 41 16 40 17 38 19 37 20 36 21 34 23 33 24 31
PAGE 410
SN74ALVCH16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES041C – JULY 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1 1OE1 1OE2 1A1 28 2OE1 2OE2 56 55 2 1Y1 2A1 29 42 To Nine Other Channels 15 2Y1 To Nine Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 411
SN74ALVCH16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES041C – JULY 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 412
SN74ALVCH16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES041C – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 413
SN74ALVCH16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES041C – JULY 1995 – REVISED FEBRUARY 1999 operating characteristics, TA = 25°C PARAMETER Outputs enabled Power dissipation capacitance Cpd VCC = 1.8 V TYP † TEST CONDITIONS CL = 50 pF, Outputs disabled f = 10 MHz VCC = 2.5 V TYP VCC = 3.3 V TYP 16 18 4 6 † UNIT pF † This information was not available at the time of publication. PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 414
SN74ALVCH16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES041C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 415
SN74ALVCH16827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES041C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 416
SN74ALVCH16828 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES042B – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D Widebus Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages 1OE1 1Y1 1Y2 GND 1Y3 1Y4 VCC 1Y5 1Y6 1Y7 GND 1Y8 1Y9 1Y10 2Y1 2Y2 2Y3 GND 2Y4 2Y5 2Y6 VCC 2Y7 2
PAGE 417
SN74ALVCH16828 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES042B – JULY 1995 – REVISED FEBRUARY 1999 logic symbol† 1 & 1OE1 1OE2 2OE1 EN1 56 28 & EN2 29 2OE2 1A1 1A2 1A3 1A4 1A5 1A6 1A7 PRODUCT PREVIEW 1A8 1A9 1A10 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 2A10 55 1 2 1 54 3 52 5 51 6 49 8 48 9 47 10 45 12 44 13 43 14 42 15 1 2 41 16 40 17 38 19 37 20 36 21 34 23 33 24 31 26 30 27 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 1Y9 1Y10 2Y1 2Y2 2Y3 2Y4 2Y5 2Y6 2Y7 2Y8 2Y9 2Y
PAGE 418
SN74ALVCH16828 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES042B – JULY 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 419
SN74ALVCH16828 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES042B – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA PRODUCT PREVIEW UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 420
SN74ALVCH16828 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES042B – JULY 1995 – REVISED FEBRUARY 1999 operating characteristics, TA = 25°C PARAMETER Outputs enabled Power dissipation capacitance Cpd VCC = 1.8 V TYP TEST CONDITIONS Outputs disabled CL = 0, VCC = 2.5 V TYP VCC = 3.3 V TYP f = 10 MHz UNIT pF PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 421
SN74ALVCH16828 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES042B – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 422
SN74ALVCH16828 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES042B – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V 1.5 V 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 423
SN74ALVCH16830 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES081B – AUGUST 1996 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Plastic 300-mil Thin Shrink Small-Outline Package 2Y2 1Y2 GND 2Y1 1Y1 VCC A1 A2 GND A3 A4 GND A5 A6 VCC A7 A8 GND A9 OE1 OE2 A10 GND A11 A12 VCC A13 A14 GND A15 A16 GND A17 A18 VCC 2Y18 1Y18 GND
PAGE 424
SN74ALVCH16830 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES081B – AUGUST 1996 – REVISED FEBRUARY 1999 logic diagram (positive logic) OE2 OE1 21 20 5 A1 1Y1 7 4 2Y1 To 17 Other Channels PRODUCT PREVIEW absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . .
PAGE 425
SN74ALVCH16830 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES081B – AUGUST 1996 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 426
SN74ALVCH16830 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES081B – AUGUST 1996 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA PRODUCT PREVIEW UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 427
SN74ALVCH16830 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES081B – AUGUST 1996 – REVISED FEBRUARY 1999 operating characteristics, TA = 25°C PARAMETER Outputs enabled Power dissipation capacitance Cpd VCC = 1.8 V TYP TEST CONDITIONS Outputs disabled CL = 0, VCC = 2.5 V TYP VCC = 3.3 V TYP f = 10 MHz UNIT pF PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 428
SN74ALVCH16830 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES081B – AUGUST 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 429
SN74ALVCH16830 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES081B – AUGUST 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V 1.5 V 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 430
SN74ALVCH16831 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES083D – AUGUST 1996 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D DBB PACKAGE (TOP VIEW) Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Pac
PAGE 431
SN74ALVCH16831 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES083D – AUGUST 1996 – REVISED FEBRUARY 1999 description (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
PAGE 432
SN74ALVCH16831 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES083D – AUGUST 1996 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 433
SN74ALVCH16831 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES083D – AUGUST 1996 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 434
SN74ALVCH16831 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES083D – AUGUST 1996 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER TO (OUTPUT) fmax VCC = 1.8 V MIN † A tpd Y CLK SEL ten tdis TYP VCC = 2.5 V ± 0.2 V MIN MAX 150 VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz † 1.2 4 4.1 1.6 3.6 † 1.1 4.5 4.4 1.5 3.9 † 1.
PAGE 435
SN74ALVCH16831 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES083D – AUGUST 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 436
SN74ALVCH16831 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES083D – AUGUST 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 437
SN74ALVCH16831 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES083D – AUGUST 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 1.5 V 0V 0V tsu 2.7 V Data Input VOLTAGE WAVEFORMS PULSE DURATION th 1.5 V 1.
PAGE 438
SN74ALVCH16832 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES098D – MAY 1997 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D DGG PACKAGE (TOP VIEW) Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Packag
PAGE 439
SN74ALVCH16832 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES098D – MAY 1997 – REVISED FEBRUARY 1999 FUNCTION TABLE INPUTS SEL CLK A OUTPUT Y H X X X Z L H X L L L H X H H L L ↑ L L L L ↑ H H OE logic diagram (positive logic) OE1 OE2 16 5 4 CLK 15 A1 2Y1 CLK 2 7 D 3Y1 Q 1 SEL 1Y1 17 4Y1 18 To Six Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . .
PAGE 440
SN74ALVCH16832 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES098D – MAY 1997 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 441
SN74ALVCH16832 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES098D – MAY 1997 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 442
SN74ALVCH16832 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES098D – MAY 1997 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER TO (OUTPUT) fmax VCC = 1.8 V MIN † A tpd Y CLK SEL ten tdis TYP VCC = 2.5 V ± 0.2 V MIN MAX 150 VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz † 1.2 4 4.1 1.6 3.6 † 1.1 4.5 4.4 1.5 3.9 † 1.3 5.
PAGE 443
SN74ALVCH16832 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES098D – MAY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 444
SN74ALVCH16832 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES098D – MAY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 445
SN74ALVCH16832 1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES098D – MAY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 1.5 V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V Output Control (low-level enabling) 2.7 V 1.5 V 1.5 V 0V tPZL 2.7 V 1.
PAGE 446
SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES140B – JULY 1998 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outlin
PAGE 447
SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES140B – JULY 1998 – REVISED FEBRUARY 1999 FUNCTION TABLE INPUTS CLK A OUTPUT Y X X X Z L X L L L L X H H L H ↑ L L L H ↑ H L H H X H Y0† OE LE H L Y0‡ † Output level before the indicated steady-state input conditions were established, provided that CLK is high before LE goes high ‡ Output level before the indicated steady-state input conditions were established L H L X logic symbol§ OE CLK 27 EN1 30 2C
PAGE 448
SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES140B – JULY 1998 – REVISED FEBRUARY 1999 logic diagram (positive logic) OE CLK LE A1 27 30 28 54 1D C1 3 Y1 CLK To 17 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . .
PAGE 449
SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES140B – JULY 1998 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 450
SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES140B – JULY 1998 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA VO = VCC or GND VI = VCC or GND, Ci One input at VCC – 0.6 V, Control inputs Data inputs IO = 0 Other inputs at VCC or GND 2.3 V 2 2.3 V 1.7 2.
PAGE 451
SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES140B – JULY 1998 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER TO (OUTPUT) fmax VCC = 1.8 V MIN † A tpd LE Y CLK ten tdis TYP VCC = 2.5 V ± 0.2 V MIN VCC = 2.7 V MAX 150 MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz † 1 4.4 4.2 1 3.6 † 1.3 6 5.9 1.5 4.9 † 1.2 6 5.
PAGE 452
SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES140B – JULY 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 453
SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES140B – JULY 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 454
SN74ALVC16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES140B – JULY 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 455
SN74ALVCH16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES190 – FEBRUARY 1999 D D D Widebus  Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages DGG, DGV, OR DL PACKAGE (TOP VIEW) NC NC Y1 GND Y2 Y3 VCC Y4 Y5 Y6 GND Y7 Y8 Y9 Y10 Y11 Y12 GND Y13 Y14 Y15 VCC Y16 Y
PAGE 456
SN74ALVCH16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES190 – FEBRUARY 1999 FUNCTION TABLE INPUTS CLK A OUTPUT Y X X X Z L X L L L L X H H L H ↑ L L L H ↑ H L H H X H Y0† OE LE H L Y0‡ † Output level before the indicated steady-state input conditions were established, provided that CLK is high before LE goes high ‡ Output level before the indicated steady-state input conditions were established L H L X PRODUCT PREVIEW logic symbol§ OE CLK 27 EN1 30 2C3 2
PAGE 457
SN74ALVCH16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES190 – FEBRUARY 1999 logic diagram (positive logic) OE CLK LE A1 27 30 28 54 1D C1 3 Y1 CLK absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 458
SN74ALVCH16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES190 – FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage PRODUCT PREVIEW IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 459
SN74ALVCH16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES190 – FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.6 V ±5 IOL = 24 mA VI = VCC or GND II(hold) MAX 1.
PAGE 460
SN74ALVCH16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES190 – FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER VCC = 1.8 V TO (OUTPUT) MIN TYP VCC = 2.5 V ± 0.2 V MIN VCC = 2.7 V MAX MIN MAX VCC = 3.3 V ± 0.
PAGE 461
SN74ALVCH16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES190 – FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 462
SN74ALVCH16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES190 – FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 463
SN74ALVCH16834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES190 – FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V 500 Ω From Output Under Test S1 GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V 1.5 V 0V tPLH 1.5 V 2.
PAGE 464
SN74ALVC16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES125D – FEBRUARY 1998 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Ideal for Use in PC100 Register DIMM Revision 1.
PAGE 465
SN74ALVC16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES125D – FEBRUARY 1998 – REVISED FEBRUARY 1999 FUNCTION TABLE INPUTS LE CLK A OUTPUT Y H X X X Z L H X L L L H X H H L L ↑ L L L L ↑ H H Y0† OE L L L or H X † Output level before the indicated steady-state input conditions were established, provided that CLK is high before LE goes low logic symbol‡ OE CLK LE 27 EN1 30 2C3 28 C3 G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 3 1 1 3D
PAGE 466
SN74ALVC16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES125D – FEBRUARY 1998 – REVISED FEBRUARY 1999 logic diagram (positive logic) OE CLK LE A1 27 30 28 54 1D C1 3 Y1 CLK To 17 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . .
PAGE 467
SN74ALVC16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES125D – FEBRUARY 1998 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 468
SN74ALVC16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES125D – FEBRUARY 1998 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA VO = VCC or GND VI = VCC or GND, Ci One input at VCC – 0.6 V, Control inputs Data inputs IO = 0 Other inputs at VCC or GND UNIT VCC–0.2 1.2 2.
PAGE 469
SN74ALVC16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES125D – FEBRUARY 1998 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER TO (OUTPUT) fmax VCC = 1.8 V MIN † TYP Y LE CLK ten tdis MIN VCC = 2.7 V MAX 150 A tpd VCC = 2.5 V ± 0.2 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz † 1 4.2 4.2 1 3.6 † 1.3 5 4.9 1.3 4.2 † 1.4 5.
PAGE 470
SN74ALVC16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES125D – FEBRUARY 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 471
SN74ALVC16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES125D – FEBRUARY 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 472
SN74ALVC16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES125D – FEBRUARY 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V 500 Ω From Output Under Test S1 GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V 1.5 V 0V tPLH 1.
PAGE 473
SN74ALVC16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES125D – FEBRUARY 1998 – REVISED FEBRUARY 1999 TYPICAL CHARACTERISTICS 0 ALVC16835 Pullup x + PC100 Requirements I OH – Output Current – mA –0.05 –0.1 –0.15 –0.2 –0.25 0.5 0 1.0 1.5 2.0 2.5 3.0 VOH – Output Voltage – V Figure 4. IV Characteristics – Pullup 0.25 ALVC16835 Pulldown x + PC100 Requirements I OL– Output Current – mA 0.20 0.15 0.10 0.05 0.00 0 0.5 1.0 1.5 2.0 2.5 3.0 VOL – Output Voltage – V Figure 5.
PAGE 474
SN74ALVCH16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES053E – SEPTEMBER 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D Widebus  Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plas
PAGE 475
SN74ALVCH16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES053E – SEPTEMBER 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE INPUTS LE CLK A OUTPUT Y H X X X Z L H X L L L H X H H L L ↑ L L L L ↑ H L L H H Y0† OE X Y0‡ † Output level before the indicated steady-state input conditions were established, provided that CLK is high before LE goes low ‡ Output level before the indicated steady-state input conditions were established L L L X logic symbol§ OE CLK LE 27 E
PAGE 476
SN74ALVCH16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES053E – SEPTEMBER 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) OE CLK LE A1 27 30 28 54 1D C1 3 Y1 CLK To 17 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . .
PAGE 477
SN74ALVCH16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES053E – SEPTEMBER 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 478
SN74ALVCH16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES053E – SEPTEMBER 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 479
SN74ALVCH16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES053E – SEPTEMBER 1995 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER VCC = 1.8 V TO (OUTPUT) MIN † fmax A tpd Y LE CLK ten tdis TYP VCC = 2.5 V ± 0.2 V MIN VCC = 2.7 V MAX 150 MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz † 1 4.2 4.2 1 3.6 † 1.3 5 4.9 1.3 4.2 † 1.4 5.
PAGE 480
SN74ALVCH16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES053E – SEPTEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 481
SN74ALVCH16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES053E – SEPTEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 482
SN74ALVCH16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES053E – SEPTEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V 500 Ω From Output Under Test S1 GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V 1.5 V 0V tPLH 1.
PAGE 483
SN74ALVCH16836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES089C – OCTOBER 1996 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D Widebus Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages OE Y1 Y
PAGE 484
SN74ALVCH16836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES089C – OCTOBER 1996 – REVISED FEBRUARY 1999 FUNCTION TABLE INPUTS CLK A OUTPUT Y X X X Z L X L L L L X H H L H ↑ L L L H ↑ H L H H X H Y0† OE LE H L Y0‡ † Output level before the indicated steady-state input conditions were established, provided that CLK is high before LE goes low ‡ Output level before the indicated steady-state input conditions were established L H L X PRODUCT PREVIEW logic symbol§ OE
PAGE 485
SN74ALVCH16836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES089C – OCTOBER 1996 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1 OE 56 CLK LE 29 55 A1 1D C1 2 Y1 CLK absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . .
PAGE 486
SN74ALVCH16836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES089C – OCTOBER 1996 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage PRODUCT PREVIEW IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 487
SN74ALVCH16836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES089C – OCTOBER 1996 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 488
SN74ALVCH16836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES089C – OCTOBER 1996 – REVISED FEBRUARY 1999 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock Clock frequency tw Pulse duration MAX VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.
PAGE 489
SN74ALVCH16836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES089C – OCTOBER 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 490
SN74ALVCH16836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES089C – OCTOBER 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 491
SN74ALVCH16836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES089C – OCTOBER 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V 1.5 V 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 492
SN74ALVCH16841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES043D – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) 1OE 1Q1 1Q2 GND 1Q3 1Q4 VCC 1Q5 1Q6 1Q7 GND 1Q8 1Q9 1Q10 2Q1 2Q2 2Q3 GND 2Q4 2Q5 2Q6 VCC 2Q7 2Q8 GND 2Q9 2Q10 2OE D Latch-Up Perform
PAGE 493
SN74ALVCH16841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES043D – JULY 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE (each 10-bit latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic symbol† 1 1OE 1LE 56 28 2OE 2LE 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 1D10 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 2D10 29 55 EN2 C1 EN4 C3 1D 54 2 2 52 5 51 6 49 8 48 9 47 10 45 12 44 13 43 14 42 15 3D 4 41 16 40 17 38 19 37 20 36 21 34 23 33
PAGE 494
SN74ALVCH16841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES043D – JULY 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1OE 1LE 1 2OE 56 2LE C1 1D1 55 2 1D 28 29 C1 1Q1 2D1 42 To Nine Other Channels 1D 15 2Q1 To Nine Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 495
SN74ALVCH16841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES043D – JULY 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 496
SN74ALVCH16841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES043D – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 497
SN74ALVCH16841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES043D – JULY 1995 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER TO (OUTPUT) D tpd Q LE ten VCC = 1.8 V Q OE tdis Q OE † This information was not available at the time of publication. VCC = 2.5 V ± 0.2 V TYP † MIN MAX 1 † VCC = 2.7 V MIN VCC = 3.3 V ± 0.3 V UNIT MAX MIN MAX 5 4.
PAGE 498
SN74ALVCH16841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES043D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 499
SN74ALVCH16841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES043D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 500
SN74ALVCH16841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES043D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 501
SN74ALVCH16843 18-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES044C – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages 1CLR 1OE 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 1Q6 GND 1Q7 1Q8 1Q9 2Q1 2Q2 2Q3 GND 2Q4 2Q5
PAGE 502
SN74ALVCH16843 18-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES044C – JULY 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE (each 9-bit latch) INPUTS PRE CLR OE LE D OUTPUT Q L X L X X H H L L X X L H H L H L L H H L H H H H H L L X Q0 X X H X X Z logic diagram (positive logic) 1OE PRODUCT PREVIEW 1PRE 1CLR 1LE 2 55 1 56 S2 1D1 C1 54 3 1Q1 1D R To Eight Other Channels 2OE 2PRE 27 30 28 2CLR 29 2LE S2 2D1 C1 42 1D R To Eight Other Channe
PAGE 503
SN74ALVCH16843 18-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES044C – JULY 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 504
SN74ALVCH16843 18-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES044C – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA PRODUCT PREVIEW UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 505
SN74ALVCH16843 18-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES044C – JULY 1995 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER TO (OUTPUT) VCC = 1.8 V TYP VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.
PAGE 506
SN74ALVCH16843 18-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES044C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 507
SN74ALVCH16843 18-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES044C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 508
SN74ALVCH16843 18-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES044C – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 0V 1.5 V 0V tsu PRODUCT PREVIEW 1.5 V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 509
SN74ALVCH16863 18-BIT TRANSCEIVER WITH 3-STATE OUTPUTS SCES060B – DECEMBER 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package
PAGE 510
SN74ALVCH16863 18-BIT TRANSCEIVER WITH 3-STATE OUTPUTS SCES060B – DECEMBER 1995 – REVISED FEBRUARY 1999 logic symbol† 56 EN1 1OEBA 1OEAB 1 EN2 29 EN3 2OEBA 2OEAB 1A1 28 EN4 55 1 1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 2A1 3 52 5 51 6 49 8 48 9 47 10 45 12 44 13 41 16 3 2A3 2A4 2A5 2A6 2A7 2A8 2A9 1B1 2 54 1 1 2A2 2 1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 2B1 4 40 17 38 19 37 20 36 21 34 23 33 24 31 26 30 27 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2B9 † This symbol is in ac
PAGE 511
SN74ALVCH16863 18-BIT TRANSCEIVER WITH 3-STATE OUTPUTS SCES060B – DECEMBER 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 512
SN74ALVCH16863 18-BIT TRANSCEIVER WITH 3-STATE OUTPUTS SCES060B – DECEMBER 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 513
SN74ALVCH16863 18-BIT TRANSCEIVER WITH 3-STATE OUTPUTS SCES060B – DECEMBER 1995 – REVISED FEBRUARY 1999 operating characteristics, TA = 25°C PARAMETER Outputs enabled Power dissipation capacitance Cpd VCC = 1.8 V TYP † TEST CONDITIONS CL = 50 pF, Outputs disabled f = 10 MHz VCC = 2.5 V TYP VCC = 3.3 V TYP 21 30 2 3 † UNIT pF † This information was not available at the time of publication. PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 514
SN74ALVCH16863 18-BIT TRANSCEIVER WITH 3-STATE OUTPUTS SCES060B – DECEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 515
SN74ALVCH16863 18-BIT TRANSCEIVER WITH 3-STATE OUTPUTS SCES060B – DECEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 516
SN74ALVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES010E – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D D D DGG PACKAGE (TOP VIEW) Widebus+ Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process UBT  (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode Simultaneously Generates and Checks Parity Option to Select Generate Parity and Check or Feed-T
PAGE 517
SN74ALVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES010E – JULY 1995 – REVISED FEBRUARY 1999 Function Tables FUNCTION† INPUTS LEAB CLKAB A OUTPUT B H X X X Z L H X L L X L H X H H L L X X H B0‡ L L L ↑ L L L L L ↑ H H L L L L X B0‡ B0§ CLKENAB OEAB X X L L L H X † A-to-B data flow is shown: B-to-A flow is similar, but uses OEBA, LEBA, and CLKENBA.
PAGE 518
SN74ALVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES010E – JULY 1995 – REVISED FEBRUARY 1999 Function Tables (Continued) PARITY INPUTS OUTPUTS SEL OEBA OEAB ODD/EVEN Σ OF INPUTS A1–A8 = H Σ OF INPUTS B1–B8 = H APAR BPAR APAR ERRA BPAR ERRB L H L L 0, 2, 4, 6, 8 N/A L N/A N/A H L Z L H L L 1, 3, 5, 7 N/A L N/A N/A L H L H L L 0, 2, 4, 6, 8 N/A H N/A N/A L L Z Z L H L L 1, 3, 5, 7 N/A H N/A N/A H H Z L L H L N/A
PAGE 519
SN74ALVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES010E – JULY 1995 – REVISED FEBRUARY 1999 functional block diagram LEAB 1CLKENAB 2CLKENAB CLKAB OEAB 2 1, 32 2 3 30 35 1A1–1A8 1APAR 1ERRB 5 61 2A1–2A8 2APAR 2ERRB ODD/EVEN SEL 28 36 18-Bit Storage 18 A-Port Parity Generate and Check B Data 18 QB 18-Bit Storage 1B1–1B8 18 QA 18 OEBA 60 B-Port Parity Generate and Check A Data 4 1BPAR 1ERRA 2B1–2B8 37 29 2BPAR 2ERRA 34 31 62 2 64, 33 63 CLKBA 1CLKENBA 2
PAGE 520
SN74ALVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES010E – JULY 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 521
SN74ALVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES010E – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 522
SN74ALVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES010E – JULY 1995 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw tsu th Clock frequency Pulse duration Setup time Hold time MAX † VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN 125 MAX VCC = 3.3 V ± 0.
PAGE 523
SN74ALVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES010E – JULY 1995 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) PARAMETER FROM (INPUT) VCC = 1.8 V TO (OUTPUT) MIN † fmax A or B APAR or BPAR ODD/EVEN SEL tpd CLKAB or CLKBA LEAB or LEBA TYP VCC = 2.5 V ± 0.2 V MIN MAX 125 VCC = 2.7 V MIN MAX 125 VCC = 3.3 V ± 0.
PAGE 524
SN74ALVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES010E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 525
SN74ALVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES010E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 526
SN74ALVCH16901 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS SCES010E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 527
SN74ALVCH16952 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES011D – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D Widebus  Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) D Latch-Up Performance Exceeds 500 mA Per D D JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plast
PAGE 528
SN74ALVCH16952 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES011D – JULY 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE† INPUTS OUTPUT B CLKENAB CLKAB OEAB A H X L X X L L X L ↑ L L L L ↑ L H H B0‡ B0‡ X X H X Z † A-to-B data flow is shown; B-to-A data flow is similar, but uses CLKENBA, CLKBA, and OEBA.
PAGE 529
SN74ALVCH16952 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES011D – JULY 1995 – REVISED FEBRUARY 1999 logic symbol† 1OEBA 56 54 1CLKENBA 1CLKBA 55 1 1OEAB 3 1CLKENAB 1CLKAB 2 29 2OEBA 31 2CLKENBA 2CLKBA 2OEAB 30 28 26 2CLKENAB 2CLKAB 1A1 27 5 EN3 G1 1C5 EN4 G2 2C6 EN9 G7 7C11 EN10 G8 8C12 3 6D 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 6 2A3 2A4 2A5 2A6 2A7 2A8 4 52 51 8 49 9 48 10 47 12 45 13 44 14 43 15 9 12D 2A2 5D 11D 42 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 2B1 10 16 41
PAGE 530
SN74ALVCH16952 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES011D – JULY 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1CLKENAB 1CLKAB 1OEBA 1A1 3 54 2 55 56 1 5 One of Eight Channels C1 CE 1D 52 1CLKENBA 1CLKBA 1OEAB 1B1 C1 CE 1D To Seven Other Channels 2CLKENAB 2CLKAB 2OEBA 26 31 27 30 29 28 One of Eight Channels 2A1 C1 CE 1D 15 C1 CE 1D To Seven Other Channels 3–438 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 42 2CLKENBA 2CLKBA 2OEAB 2B1
PAGE 531
SN74ALVCH16952 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES011D – JULY 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 532
SN74ALVCH16952 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES011D – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA UNIT VCC–0.2 1.2 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 0.45 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.
PAGE 533
SN74ALVCH16952 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES011D – JULY 1995 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER fmax tpd ten TO (OUTPUT) VCC = 1.8 V MIN † TYP VCC = 2.5 V ± 0.2 V MIN MAX 150 VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz CLK A or B † 1 4.1 4.6 1 3.9 ns OEBA or OEAB A or B † 1 5.4 5.3 1 4.
PAGE 534
SN74ALVCH16952 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES011D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 535
SN74ALVCH16952 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES011D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 536
SN74ALVCH16952 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS SCES011D – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 537
SN74ALVCH32501 36-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES144A – OCTOBER 1998 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D Bus Hold on Data Inputs Eliminates the Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process UBT  (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode D Need for External Pullup/Pulldown Resistors Packaged in Plastic Fine-Pitch Ball Grid Array Pac
PAGE 538
PRODUCT PREVIEW 6 5 4 3 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 A B C D E F G H J K L M N P R T U V W terminal assignments 6 1B2 1B4 1B6 1B8 1B10 1B12 1B14 1B15 1B17 NC 2B2 2B4 2B6 2B8 2B10 2B12 2B14 2B15 2B17 5 1B1 1B3 1B5 1B7 1B9 1B11 1B13 1B16 1B18 2CLKAB 2B1 2B3 2B5 2B7 2B9 2B11 2B13 2B16 2B18 4 1CLKAB GND GND GND 1CLKBA GND GND GND GND 2CLKBA GND GND GND GND 1OEBA 1LEBA 2OEAB GND GND GND VCC VCC GND GND VCC VC
PAGE 539
SN74ALVCH32501 36-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES144A – OCTOBER 1998 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1CLKAB 1LEAB 1LEBA 1CLKBA 1OEBA 1A1 B3 A4 A3 K3 J4 J3 A2 1D C1 CLK A5 1B1 PRODUCT PREVIEW 1OEAB 1D C1 CLK To 17 Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3–447
PAGE 540
SN74ALVCH32501 36-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES144A – OCTOBER 1998 – REVISED FEBRUARY 1999 logic diagram (positive logic) 2OEAB 2CLKAB 2LEAB 2LEBA 2CLKBA 2OEBA PRODUCT PREVIEW 2A1 L3 K5 K2 W3 V4 V3 L2 1D C1 CLK L5 2B1 1D C1 CLK To 17 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 541
SN74ALVCH32501 36-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES144A – OCTOBER 1998 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V Low-level output current VCC = 2.
PAGE 542
SN74ALVCH32501 36-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES144A – OCTOBER 1998 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 µA PRODUCT PREVIEW 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 V 0.2 2.3 V 0.4 2.3 V 0.7 2.7 V 0.4 3V 0.55 3.6 V ±5 VI = 0.
PAGE 543
SN74ALVCH32501 36-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES144A – OCTOBER 1998 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock Clock frequency tw Pulse duration MAX VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.
PAGE 544
SN74ALVCH32501 36-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES144A – OCTOBER 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 545
SN74ALVCH32501 36-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES144A – OCTOBER 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 546
SN74ALVCH32501 36-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES144A – OCTOBER 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V 0V 0V tsu PRODUCT PREVIEW 1.5 V Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 547
General Information ALVC Gates/Octals ALVC Widebus/Widebus+ ALVC Widebus With Series Damping Resistors ALVC Dual-Supply-Voltage Translators SSTL HSTL ALB Mechanical Data A Output Derating Curves 4–1
PAGE 548
Contents Page ALVC Widebus With Series Damping Resistors SN74ALVCH162244 SN74ALVCHR162245 SN74ALVCH162260 SN74ALVCH162268 SN74ALVCHR162282 SN74ALVC162334 SN74ALVCH162334 SN74ALVCH162344 SN74ALVCH162374 SN74ALVCH162409 SN74ALVCHR162409 SN74ALVCH162525 SN74ALVCH162601 SN74ALVCHR16601 SN74ALVCHR16269A SN74ALVCH162721 SN74ALVCH162820 SN74ALVCH162827 SN74ALVCH162830 SN74ALVC162831 SN74ALVCH162831 SN74ALVCH162832 SN74ALVC162834 SN74ALVC162835 SN74ALVCH162835 SN74ALVC162836 SN74ALVCH162836 SN74ALVCH162841 4–2
PAGE 549
SN74ALVCH162244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES065C – JANUARY 1996 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD
PAGE 550
SN74ALVCH162244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES065C – JANUARY 1996 – REVISED FEBRUARY 1999 FUNCTION TABLE (each 4-bit buffer) INPUTS OE A OUTPUT Y L H H L L L H X Z logic symbol† 1OE 2OE 1 EN1 48 25 3OE 4OE 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 24 EN2 EN3 EN4 47 1 1 46 3 44 5 43 6 41 8 40 1 2 9 38 11 37 12 36 13 35 1 3 14 33 16 32 17 30 1 4 19 29 20 27 22 26 23 † This symbol is in accordance with ANSI/IEEE St
PAGE 551
SN74ALVCH162244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES065C – JANUARY 1996 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 1 3OE 47 2 46 3 44 5 43 6 1Y1 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 48 4OE 41 8 40 9 38 11 37 12 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 25 36 13 35 14 33 16 32 17 3Y1 3Y2 3Y3 3Y4 24 30 19 29 20 27 22 26 23 4Y1 4Y2 4Y3 4Y4 absolute maximum ratings over operating free-air temperat
PAGE 552
SN74ALVCH162244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES065C – JANUARY 1996 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC VCC VCC = 1.65 V VCC = 2.3 V –2 VCC = 2.7 V VCC = 3 V –8 –6 V V mA –12 VCC = 1.65 V VCC = 2.
PAGE 553
SN74ALVCH162244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES065C – JANUARY 1996 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 4 mA IOL = 6 mA IOL = 8 mA IOL = 12 mA II VI = VCC or GND VI = 0.
PAGE 554
SN74ALVCH162244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES065C – JANUARY 1996 – REVISED FEBRUARY 1999 operating characteristics, TA = 25°C PARAMETER Outputs enabled Power dissipation capacitance Cpd VCC = 1.8 V TYP † TEST CONDITIONS Outputs disabled CL = 50 pF, f = 10 MHz VCC = 2.5 V TYP VCC = 3.3 V TYP 16 19 4 5 † UNIT pF † This information was not available at the time of publication. PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 555
SN74ALVCH162244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES065C – JANUARY 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 556
SN74ALVCH162244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES065C – JANUARY 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 557
SN74ALVCHR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES064C – DECEMBER 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process All Outputs Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per J
PAGE 558
SN74ALVCHR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES064C – DECEMBER 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE (each 8-bit section) INPUTS OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation logic symbol† 48 1OE 1DIR 1 G3 3 EN1 [BA] 3 EN2 [AB] 25 2OE 2DIR 24 G6 6 EN4 [BA] 6 EN5 [AB] 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 47 2 1 2 46 5 43 6 41 8 40 9 38 11 37 12 36 13 4 35 5 14 33 16 32 17 30 19 29 20
PAGE 559
SN74ALVCHR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES064C – DECEMBER 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 24 2OE 36 13 1B1 2B1 To Seven Other Channels To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 560
SN74ALVCHR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES064C – DECEMBER 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC VCC VCC = 1.65 V VCC = 2.3 V –2 VCC = 2.7 V VCC = 3 V –8 –6 V V mA –12 VCC = 1.65 V VCC = 2.
PAGE 561
SN74ALVCHR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES064C – DECEMBER 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 4 mA 0.4 2.3 V 0.55 3V 0.55 IOL = 8 mA IOL = 12 mA 2.7 V 0.6 3V 0.
PAGE 562
SN74ALVCHR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES064C – DECEMBER 1995 – REVISED FEBRUARY 1999 operating characteristics, TA = 25°C PARAMETER Outputs enabled Power dissipation capacitance Cpd VCC = 1.8 V TYP † TEST CONDITIONS CL = 50 pF, Outputs disabled f = 10 MHz VCC = 2.5 V TYP VCC = 3.3 V TYP 24 32 4 5 † UNIT pF † This information was not available at the time of publication. PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 563
SN74ALVCHR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES064C – DECEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 564
SN74ALVCHR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES064C – DECEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V From Output Under Test 6V Open S1 500 Ω GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 565
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS570G – MARCH 1996 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process B-Port Outputs Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Ex
PAGE 566
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS570G – MARCH 1996 – REVISED FEBRUARY 1999 Function Tables B TO A (OEB = H) INPUTS 1B 2B SEL LE1B LE2B OEA OUTPUT A H X H H X L H L X H H X L L X X H L X L X H L X H L A0 H X L L X H L L X X L X L L X X X X X H A0 Z A TO B (OEA = H) INPUTS 4–20 LEA2B OUTPUTS A LEA1B OE1B OE2B 1B 2B H H H L H H L L H H L L L H H L L L L H 2B0 2B0 L H L L L
PAGE 567
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS570G – MARCH 1996 – REVISED FEBRUARY 1999 logic diagram (positive logic) LE1B LE2B LEA1B LEA2B OE2B OE1B OEA SEL A1 2 27 30 55 56 29 1 28 G1 C1 1 1D 8 23 1B1 1 C1 1D 6 2B1 C1 1D C1 1D To 11 Other Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–21
PAGE 568
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS570G – MARCH 1996 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 569
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS570G – MARCH 1996 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage MAX 1.65 3.6 2 0.35 × VCC 0.
PAGE 570
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS570G – MARCH 1996 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA A port IOH = –12 mA IOH = –24 mA IOH = –100 µA VOH A port 2.4 2 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 4 mA 1.65 V to 3.6 V 0.2 1.65 V 0.
PAGE 571
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS570G – MARCH 1996 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN MAX † VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN 150 MAX VCC = 3.3 V ± 0.3 V MIN UNIT MAX fclock Clock frequency 150 150 MHz tw Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high † 3.3 3.3 3.
PAGE 572
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS570G – MARCH 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 573
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS570G – MARCH 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 574
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS570G – MARCH 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V From Output Under Test 6V Open S1 500 Ω GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 575
SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018F – AUGUST 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process B-Port Outputs Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus
PAGE 576
SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018F – AUGUST 1995 – REVISED FEBRUARY 1999 description (continued) Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH162268 is characterized for operation from –40°C to 85°C.
PAGE 577
SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018F – AUGUST 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) 29 CLK 2 CLKEN1B 27 CLKEN2B CLKENA1 30 55 C1 CLKENA2 56 1D OEB C1 SEL 28 1D 1 OEA CE 1D C1 1D C1 G1 A1 1 1B1 CE C1 1 8 23 1D 1D 6 2B1 CE CE C1 C1 1D 1D CE C1 1D 1 of 12 Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–31
PAGE 578
SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018F – AUGUST 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 579
SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018F – AUGUST 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage MAX 1.65 3.6 2 0.35 × VCC 0.
PAGE 580
SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018F – AUGUST 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA A port IOH = –12 mA IOH = –24 mA IOH = –100 µA VOH A port 2.4 2 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 4 mA 1.65 V to 3.6 V 0.2 1.65 V 0.
PAGE 581
SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018F – AUGUST 1995 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw tsu th Clock frequency Hold time MIN MAX VCC = 2.7 V MIN 120 MAX VCC = 3.3 V ± 0.3 V MIN 150 3.3 3.3 3.3 A data before CLK↑ † 4.5 4 3.4 B data before CLK↑ † 0.8 1.2 1 SEL before CLK↑ † 1.4 1.6 1.
PAGE 582
SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018F – AUGUST 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 583
SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018F – AUGUST 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 584
SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018F – AUGUST 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 1.5 V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V Output Control (low-level enabling) 2.7 V 1.5 V 1.5 V 0V tPZL 2.7 V 1.
PAGE 585
SN74ALVCHR162282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES087A – SEPTEMBER 1996 – REVISED FEBRUARY 1999 D EPIC (Enhanced-Performance Implanted D D D CMOS) Sub-Micron Process Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Member of the Texas Instruments Widebus Family Bus-Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Packaged in Thin Shrink Small-Outline Package VCC GND 2B9 1B9 2B8 GND 1B8 2B7 1B7 VCC
PAGE 586
SN74ALVCHR162282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES087A – SEPTEMBER 1996 – REVISED FEBRUARY 1999 Function Tables A-TO-B STORAGE (OE = L, DIR = H) INPUTS OUTPUTS SEL CLK A 1B 2B H X X L ↑ L 1B0† L‡ 2B0† X ↑ H H‡ X † Output level before the indicated steady-state input conditions are established ‡ Two CLK edges are needed to propagate the data.
PAGE 587
SN74ALVCHR162282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES087A – SEPTEMBER 1996 – REVISED FEBRUARY 1999 logic diagram (positive logic) CLK SEL OE 39 40 42 CE C1 1D 1D 25 1B1 G1 CE C1 A1 27 1 1D 1 C1 1D 1D 24 2B1 CE C1 1D C1 1D CE C1 1D 1 of 18 Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–41 PRODUCT PREVIEW DIR 41
PAGE 588
SN74ALVCHR162282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES087A – SEPTEMBER 1996 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
PAGE 589
SN74ALVCHR162282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES087A – SEPTEMBER 1996 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 4 mA 0.4 2.3 V 0.55 3V 0.55 IOL = 8 mA IOL = 12 mA 2.7 V 0.
PAGE 590
SN74ALVCHR162282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES087A – SEPTEMBER 1996 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw MAX VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.
PAGE 591
SN74ALVCHR162282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES087A – SEPTEMBER 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 592
SN74ALVCHR162282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES087A – SEPTEMBER 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V " 0.2 V 4.6 V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 4.6 V GND tw LOAD CIRCUIT 2.3 V 2.3 V Timing Input 1.2 V 0V 0V tsu PRODUCT PREVIEW 1.2 V Input 1.2 V VOLTAGE WAVEFORMS PULSE DURATION th 2.3 V Data Input 1.2 V 1.
PAGE 593
SN74ALVCHR162282 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES087A – SEPTEMBER 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V " 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V 1.5 V Input 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 594
SN74ALVC162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES127C – FEBRUARY 1998 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Ideal for Use in PC100 Register DIMM Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification ESD Protection Exceeds
PAGE 595
SN74ALVC162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES127C – FEBRUARY 1998 – REVISED FEBRUARY 1999 FUNCTION TABLE INPUTS CLK A OUTPUT Y X X X Z L X L L L L X H H L H ↑ L L L H ↑ H H Y0† OE LE H L L H L or H X † Output level before the indicated steady-state input conditions were established logic symbol‡ OE CLK LE 1 EN1 48 25 2C3 C3 G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 2 3 1 1 3D 46 5 44 6 43 1 8 41 9 40 11 38 12 37 13
PAGE 596
SN74ALVC162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES127C – FEBRUARY 1998 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1 OE 48 CLK LE 25 47 A1 1D C1 2 Y1 CLK To 15 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . .
PAGE 597
SN74ALVC162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES127C – FEBRUARY 1998 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC VCC VCC = 1.65 V VCC = 2.3 V –2 VCC = 2.7 V VCC = 3 V –8 –6 V V mA –12 VCC = 1.65 V VCC = 2.
PAGE 598
SN74ALVC162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES127C – FEBRUARY 1998 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA TYP† MAX 1.65 V VCC–0.2 1.2 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.
PAGE 599
SN74ALVC162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES127C – FEBRUARY 1998 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER TO (OUTPUT) fmax VCC = 1.8 V MIN † A tpd Y LE CLK ten tdis VCC = 2.5 V ± 0.2 V TYP MIN VCC = 2.7 V MAX 150 MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz † 1 4.4 4.5 1.1 † 1 5.8 6 1.3 5 † 1 5.2 5.
PAGE 600
SN74ALVC162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES127C – FEBRUARY 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 601
SN74ALVC162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES127C – FEBRUARY 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 602
SN74ALVC162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES127C – FEBRUARY 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 603
SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES120E – JULY 1997 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Output Port Has Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Excee
PAGE 604
SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES120E – JULY 1997 – REVISED FEBRUARY 1999 FUNCTION TABLE INPUTS CLK A OUTPUT Y X X X Z L X L L L L X H H L H ↑ L L L H ↑ H H Y0† OE LE H L L H L or H X † Output level before the indicated steady-state input conditions were established logic symbol‡ OE CLK LE 1 EN1 48 25 2C3 C3 G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 2 1 1 3D 3 46 5 44 6 43 1 8 41 9 40 11 38 12 37 13
PAGE 605
SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES120E – JULY 1997 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1 OE 48 CLK LE 25 47 A1 1D C1 2 Y1 CLK To 15 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . .
PAGE 606
SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES120E – JULY 1997 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC VCC VCC = 1.65 V VCC = 2.3 V –2 VCC = 2.7 V VCC = 3 V –8 –6 V V mA –12 VCC = 1.65 V VCC = 2.
PAGE 607
SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES120E – JULY 1997 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 4 mA IOL = 6 mA IOL = 8 mA IOL = 12 mA II VI = VCC or GND VI = 0.
PAGE 608
SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES120E – JULY 1997 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw tsu Clock frequency Pulse duration Setup time MIN MAX MIN 150 MAX VCC = 3.3 V ± 0.3 V MIN 150 LE low 3.3 3.3 3.3 † 3.3 3.3 3.3 Data before CLK↑ † 1.4 1.7 1.5 CLK high † 1.2 1.6 1.3 CLK low † 1.4 1.5 1.2 † 0.9 0.
PAGE 609
SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES120E – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 610
SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES120E – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 611
SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES120E – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 612
SN74ALVCH162344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES085E – AUGUST 1996 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options
PAGE 613
SN74ALVCH162344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES085E – AUGUST 1996 – REVISED FEBRUARY 1999 logic diagram (positive logic) OE4 OE3 OE2 OE1 56 29 28 1 2 3 1A 5A 6 9 10 13 16 17 41 2B1 40 2B2 23 38 37 2B4 48 3B1 47 3B2 24 45 44 3B4 55 4B1 54 4B2 8A 26 27 5B4 6B1 6B2 6B3 6B4 7B1 7B2 7B3 7B4 8B1 8B2 49 52 4B3 51 4B4 POST OFFICE BOX 655303 5B3 43 3B3 21 5B2 42 2B3 7A 20 4–70 30 1B4 15 19 4A 31 6A 5B1 36 1B3 14 12 3A 33
PAGE 614
SN74ALVCH162344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES085E – AUGUST 1996 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 615
SN74ALVCH162344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES085E – AUGUST 1996 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 4 mA IOL = 6 mA IOL = 8 mA IOL = 12 mA II VI = VCC or GND VI = 0.
PAGE 616
SN74ALVCH162344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES085E – AUGUST 1996 – REVISED FEBRUARY 1999 operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS Outputs enabled Power dissipation capacitance Cpd CL = 0, Outputs disabled VCC = 1.8 V TYP † f = 10 MHz VCC = 2.5 V TYP † VCC = 3.3 V TYP 68 82 12 14 UNIT pF † This information was not available at the time of publication. PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 617
SN74ALVCH162344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES085E – AUGUST 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 618
SN74ALVCH162344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES085E – AUGUST 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 619
SN74ALVCH162374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES092B – JANUARY 1997 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required ESD Protection Exceeds 2000 V Per MIL-STD-833, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Excee
PAGE 620
SN74ALVCH162374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES092B – JANUARY 1997 – REVISED FEBRUARY 1999 FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z logic symbol† 1OE 1CLK 2OE 2CLK 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 1 1EN 48 C1 24 2EN 25 C2 47 1D 2 1 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 2D 2 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1Q1 1Q
PAGE 621
SN74ALVCH162374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES092B – JANUARY 1997 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
PAGE 622
SN74ALVCH162374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES092B – JANUARY 1997 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.
PAGE 623
SN74ALVCH162374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES092B – JANUARY 1997 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER fmax tpd CLK ten OE TO (OUTPUT) VCC = 1.8 V MIN † VCC = 2.5 V ± 0.2 V TYP MIN MAX 150 VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz Q † 1 5.4 5.4 1 4.6 ns Q † 1 6.5 6.4 1 5.
PAGE 624
SN74ALVCH162374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES092B – JANUARY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 625
SN74ALVCH162374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES092B – JANUARY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 626
SN74ALVCH162374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES092B – JANUARY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 627
SN74ALVCH162409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES189 – FEBRUARY 1999 D Member of the Texas Instruments D D D D D D Widebus+ Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process B-Port Outputs Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required UBE  (Universal Bus Exchanger) Allows Synchronous Data Exchange ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Perf
PAGE 628
SN74ALVCH162409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES189 – FEBRUARY 1999 Function Tables INPUTS CLK SEND PORT X X OUTPUT RECEIVE PORT X L B0† L X H H ↑ L L ↑ H H X H B0† X B0† † Output level before the indicated steady-state input conditions were established L DATA-FLOW CONTROL INPUTS PRODUCT PREVIEW PRE 4–86 SEL1 SEL2 CLK SEL0 H X X X X X X X L H ↑ X X X X X No change L L ↑ 0 0 0 0 0 None, all I/Os off L L ↑ 0 0 0 0 1
PAGE 629
SN74ALVCH162409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES189 – FEBRUARY 1999 logic diagram (positive logic) SELEN 1 56 PRE 55 28 SEL2 2 29 SEL0 SEL1 SEL3 Flow and Storage Control 30 27 SEL4 3 3 2Ax 1Ax CLK D 1A 1Ax CLK D 2A CLK D 1Bx 2Ax 2Bx 2Bx 3 1B 1Bx 3 1Ax 1Ax 1Bx 2Bx 2Ax 1Bx CLK D 2Ax 2B 2Bx One of Nine Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . .
PAGE 630
SN74ALVCH162409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES189 – FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage 1.65 3.6 Output voltage High-level output current (B port) Low-level output current (A port) IOL Low-level output current (B port) 2 0.35 × VCC 0.
PAGE 631
SN74ALVCH162409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES189 – FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA A port IOH = –12 mA IOH = –24 mA IOH = –100 µA VOH A port 2.4 2 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 4 mA 1.65 V to 3.6 V 0.2 1.65 V 0.45 2.3 V 0.4 2.3 V 0.
PAGE 632
SN74ALVCH162409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES189 – FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw MAX VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.
PAGE 633
SN74ALVCH162409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES189 – FEBRUARY 1999 timing diagram CLK tsu th tsu th SELEN ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tsu Selected Input Port Selected Output Port ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ th ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ PRODUCT PREVIEW SEL (0-4) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tpd CLK to Output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–91
PAGE 634
SN74ALVCH162409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES189 – FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 635
SN74ALVCH162409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES189 – FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 636
SN74ALVCH162409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES189 – FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 1.5 V PRODUCT PREVIEW 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V Output Control (low-level enabling) 2.7 V 1.5 V 1.5 V 0V tPZL 2.7 V 1.
PAGE 637
SN74ALVCHR162409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056F – SEPTEMBER 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus+ Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process B-Port Outputs Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required UBE  (Universal Bus Exchanger) Allows Synchronous Data Exchange ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 2
PAGE 638
SN74ALVCHR162409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056F – SEPTEMBER 1995 – REVISED FEBRUARY 1999 Function Tables INPUTS CLK SEND PORT X X OUTPUT RECEIVE PORT X L B0† L X H H ↑ L L ↑ H H X H B0† X B0† † Output level before the indicated steady-state input conditions were established L DATA-FLOW CONTROL INPUTS PRE 4–96 SEL1 SEL2 CLK SEL0 H X X X X X X X L H ↑ X X X X X No change L L ↑ 0 0 0 0 0 None, all I/Os off L L ↑ 0 0
PAGE 639
SN74ALVCHR162409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056F – SEPTEMBER 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) CLK SELEN 1 56 PRE 55 28 SEL2 2 29 SEL0 SEL1 SEL3 Flow and Storage Control 30 27 SEL4 3 3 2Ax 1Ax CLK D 1A 1Ax CLK D 2A CLK D 1Bx 2Ax 2Bx 2Bx 3 1B 1Bx 3 1Ax 1Ax 1Bx 2Bx 2Ax 1Bx CLK D 2Ax 2B 2Bx One of Nine Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage ra
PAGE 640
SN74ALVCHR162409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056F – SEPTEMBER 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC VCC VCC = 1.65 V VCC = 2.3 V –2 VCC = 2.7 V VCC = 3 V –8 –6 V V mA –12 VCC = 1.
PAGE 641
SN74ALVCHR162409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056F – SEPTEMBER 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 4 mA 0.4 2.3 V 0.55 3V 0.55 IOL = 8 mA IOL = 12 mA 2.
PAGE 642
SN74ALVCHR162409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056F – SEPTEMBER 1995 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw tsu th Clock frequency Hold time MIN MAX VCC = 2.7 V MIN 120 MAX VCC = 3.3 V ± 0.3 V MIN 120 4.2 4.2 3 A or B before CLK↑ † 1.9 1.9 1.4 SEL before CLK↑ † 5.1 4.2 3.5 SELEN before CLK↑ † 2.5 2.5 1.
PAGE 643
SN74ALVCHR162409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056F – SEPTEMBER 1995 – REVISED FEBRUARY 1999 timing diagram CLK tsu th tsu th SELEN SEL (0-4) ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tsu Selected Input Port Selected Output Port ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ th ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tpd CLK to Output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–101
PAGE 644
SN74ALVCHR162409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056F – SEPTEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 645
SN74ALVCHR162409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056F – SEPTEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 646
SN74ALVCHR162409 9-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS SCES056F – SEPTEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 1.5 V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V Output Control (low-level enabling) 2.7 V 1.5 V 1.5 V 0V tPZL 2.7 V 1.
PAGE 647
SN74ALVCH162525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES058D – NOVEMBER 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process B-Port Outputs Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold o
PAGE 648
SN74ALVCH162525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES058D – NOVEMBER 1995 – REVISED FEBRUARY 1999 Function Tables A-TO-B STORAGE (OEAB = L) INPUTS CLKENAB CLKAB A H X X L ↑ L L ↑ H OUTPUT B B0† L H † Output level before the indicated steady-state input conditions were established B-TO-A STORAGE (OEBA = L) INPUTS CLKENBA CLK2BA CLK1BA SEL B H X X X X L ↑ X H L L ↑ X H H L ↑ ↑ L ↑ ↑ L L OUTPUT A A0† L H L‡ H‡ † Output level before the indicated
PAGE 649
SN74ALVCH162525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES058D – NOVEMBER 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) CLKAB CLK1BA CLK2BA CLKENBA CLKENAB OEAB OEBA SEL 55 30 29 28 1 2 27 56 1 of 18 Channels G1 CE 3 A1 C1 1D CE 1 1 C1 1D CE C1 1D CE C1 1D 54 B1 CE C1 1D POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–107
PAGE 650
SN74ALVCH162525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES058D – NOVEMBER 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 651
SN74ALVCH162525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES058D – NOVEMBER 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage MAX 1.65 3.6 2 0.35 × VCC 0.
PAGE 652
SN74ALVCH162525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES058D – NOVEMBER 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA A port IOH = –12 mA IOH = –24 mA IOH = –100 µA VOH A port 2.4 2 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 4 mA 1.65 V to 3.6 V 0.2 1.65 V 0.45 2.
PAGE 653
SN74ALVCH162525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES058D – NOVEMBER 1995 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 2.5 V ± 0.2 V VCC = 1.8 V MIN fclock tw tsu th Clock frequency Hold time MIN MAX MIN 120 MAX VCC = 3.3 V ± 0.3 V MIN 150 3.2 3.2 3 A data before CLKAB↑ † 1.3 1.3 1.3 B data before CLK2BA↑ † 2.1 1.8 1.7 B data before CLK1BA↑ † 1.
PAGE 654
SN74ALVCH162525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES058D – NOVEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 655
SN74ALVCH162525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES058D – NOVEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 656
SN74ALVCH162525 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES058D – NOVEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V From Output Under Test 6V Open S1 500 Ω GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 657
SN74ALVCH162601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES026F – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process UBT  (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode B-Port Outputs Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required E
PAGE 658
SN74ALVCH162601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES026F – JULY 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE† INPUTS OUTPUT B CLKENAB OEAB LEAB CLKAB A X H X X X Z X L H X L L X L H X H H H L L X X H L L X X B0‡ B0‡ L L L ↑ L L L L L ↑ H H B0‡ L L L L or H X † A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA.
PAGE 659
SN74ALVCH162601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES026F – JULY 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 660
SN74ALVCH162601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES026F – JULY 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage MAX 1.65 3.6 2 0.35 × VCC 0.
PAGE 661
SN74ALVCH162601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES026F – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA A port IOH = –12 mA IOH = –24 mA IOH = –100 µA VOH A port 2.4 2 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 4 mA 1.65 V to 3.6 V 0.2 1.65 V 0.45 2.
PAGE 662
SN74ALVCH162601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES026F – JULY 1995 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw tsu th Clock frequency Pulse duration Setup time Hold time MAX † VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN 140 MAX VCC = 3.3 V ± 0.3 V MIN 150 150 LE high † 3.3 3.3 3.3 CLK high or low † 3.3 3.3 3.
PAGE 663
SN74ALVCH162601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES026F – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 664
SN74ALVCH162601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES026F – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 665
SN74ALVCH162601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES026F – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 666
SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES123F – SEPTEMBER 1997 – REVISED MARCH 1999 D Member of the Texas Instruments D D D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process UBT  (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Ar
PAGE 667
SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES123F – SEPTEMBER 1997 – REVISED MARCH 1999 description (continued) Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCHR16601 is characterized for operation from –40°C to 85°C.
PAGE 668
SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES123F – SEPTEMBER 1997 – REVISED MARCH 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 669
SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES123F – SEPTEMBER 1997 – REVISED MARCH 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 4 mA 0.4 2.3 V 0.55 3V 0.55 IOL = 8 mA IOL = 12 mA 2.7 V 0.
PAGE 670
SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES123F – SEPTEMBER 1997 – REVISED MARCH 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock Clock frequency Pulse duration tw tsu Setup time th Hold time VCC = 2.5 V ± 0.2 V MAX † MIN MAX VCC = 2.7 V MIN 150 MAX VCC = 3.3 V ± 0.3 V MIN 150 150 LE high † 3.3 3.3 3.3 CLK high or low † 3.3 3.3 3.
PAGE 671
SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES123F – SEPTEMBER 1997 – REVISED MARCH 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 672
SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES123F – SEPTEMBER 1997 – REVISED MARCH 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 673
SN74ALVCHR16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES123F – SEPTEMBER 1997 – REVISED MARCH 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V Input 1.
PAGE 674
SN74ALVCHR16269A 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES050K – AUGUST 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process All Outputs Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors ESD Protection Exceeds 2000 V Per MIL-STD-883, Met
PAGE 675
SN74ALVCHR16269A 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES050K – AUGUST 1995 – REVISED FEBRUARY 1999 description (continued) All outputs are designed to sink up to 12 mA and include equivalent 26-Ω resistors to reduce overshoot and undershoot. The SN74ALVCHR16269A is characterized for operation from –40°C to 85°C.
PAGE 676
SN74ALVCHR16269A 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES050K – AUGUST 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) CLK OEB1 29 C1 2 1D C1 OEB2 CLKENA1 CLKENA2 56 1D 30 55 C1 SEL OEA 28 1D 1 1D 1 of 12 Channels C1 G1 A1 8 C1 1 1D 23 1B1 1 CE C1 1D 6 2B1 CE C1 1D POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–135
PAGE 677
SN74ALVCHR16269A 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES050K – AUGUST 1995 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 678
SN74ALVCHR16269A 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES050K – AUGUST 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 4 mA 0.4 2.3 V 0.55 3V 0.
PAGE 679
SN74ALVCHR16269A 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES050K – AUGUST 1995 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw tsu th Clock frequency Hold time MAX † MIN MAX VCC = 2.7 V MIN 95 MAX VCC = 3.3 V ± 0.3 V MIN 135 5.2 4.3 3.3 A data before CLK↑ † 1.4 1.4 1 B data before CLK↑ † 1.6 1.5 1.1 SEL before CLK↑ † 0.8 1.1 1.
PAGE 680
SN74ALVCHR16269A 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES050K – AUGUST 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 681
SN74ALVCHR16269A 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES050K – AUGUST 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 682
SN74ALVCHR16269A 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES050K – AUGUST 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 1.5 V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0V tPLH Output Control (low-level enabling) 1.
PAGE 683
SN74ALVCH162721 3.
PAGE 684
SN74ALVCH162721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCES055D – DECEMBER 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE (each flip-flop) INPUTS OE CLKEN CLK D OUTPUT Q L H X X Q0 L L ↑ H H L L ↑ L L L L L or H X Q0 H X X X Z logic diagram (positive logic) 1 OE 56 CLK 29 CE CLKEN C1 D1 55 1D 2 Q1 To 19 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . .
PAGE 685
SN74ALVCH162721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCES055D – DECEMBER 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC VCC VCC = 1.65 V VCC = 2.3 V –2 VCC = 2.7 V VCC = 3 V –8 –6 V V mA –12 VCC = 1.65 V VCC = 2.
PAGE 686
SN74ALVCH162721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCES055D – DECEMBER 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.
PAGE 687
SN74ALVCH162721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCES055D – DECEMBER 1995 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER fmax tpd CLK ten OE VCC = 1.8 V TO (OUTPUT) MIN † TYP VCC = 2.5 V ± 0.2 V MIN MAX 150 VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz Q † 1 6.7 6.2 1 5.3 ns Q † 1 7.2 7 1 5.8 ns † 1 6.3 5.
PAGE 688
SN74ALVCH162721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCES055D – DECEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 689
SN74ALVCH162721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCES055D – DECEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 690
SN74ALVCH162721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS SCES055D – DECEMBER 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 1.5 V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 0V tPLH Output Output Control (low-level enabling) 2.7 V 1.5 V 1.5 V 0V tPZL 2.7 V 1.
PAGE 691
SN74ALVCH162820 3.
PAGE 692
SN74ALVCH162820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS SCES012E – JULY 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE (each flip-flop) INPUTS OEn† L CLK D OUTPUT Q ↑ H H L ↑ L L L L X Q0 H † n = 1, 2 X X Z logic diagram (positive logic) 1OE 2OE CLK 1 28 56 2 1Q1 C1 D1 55 3 1D 1Q2 To Nine Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . .
PAGE 693
SN74ALVCH162820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS SCES012E – JULY 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC VCC VCC = 1.65 V VCC = 2.3 V –2 VCC = 2.7 V VCC = 3 V –8 –6 V V mA –12 VCC = 1.
PAGE 694
SN74ALVCH162820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS SCES012E – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.
PAGE 695
SN74ALVCH162820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS SCES012E – JULY 1995 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER fmax tpd ten tdis VCC = 1.8 V TO (OUTPUT) MIN † TYP VCC = 2.5 V ± 0.2 V MIN MAX 150 VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz CLK Q † 1 6.4 6.2 1 5.4 ns OE Q † 1 6.9 6.8 1 5.
PAGE 696
SN74ALVCH162820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS SCES012E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 697
SN74ALVCH162820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS SCES012E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 698
SN74ALVCH162820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS SCES012E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 0V 0V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) 2.7 V 1.5 V 1.5 V 0V tPLZ tPZL 2.7 V 1.
PAGE 699
SN74ALVCH162827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES013E – JULY 1995 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per J
PAGE 700
SN74ALVCH162827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES013E – JULY 1995 – REVISED FEBRUARY 1999 FUNCTION TABLE (each 10-bit section) INPUTS OE1 OE2 A OUTPUT Y L L L L L L H H H X X Z X H X Z logic symbol† 1OE1 1OE2 2OE1 2OE2 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1A10 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9 2A10 1 & EN1 56 28 & EN2 29 55 1 1 3 52 5 51 6 49 8 48 9 47 10 45 12 44 13 43 14 42 1 2 15 41 16 40 17 38 19 37 20 36 21 34 23 33 24 31 26
PAGE 701
SN74ALVCH162827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES013E – JULY 1995 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1 1OE1 1OE2 1A1 28 2OE1 2OE2 56 55 2 1Y1 2A1 29 42 To Nine Other Channels 15 2Y1 To Nine Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 702
SN74ALVCH162827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES013E – JULY 1995 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC VCC VCC = 1.65 V VCC = 2.3 V –2 VCC = 2.7 V VCC = 3 V –8 –6 V V mA –12 VCC = 1.65 V VCC = 2.
PAGE 703
SN74ALVCH162827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES013E – JULY 1995 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 4 mA IOL = 6 mA IOL = 8 mA IOL = 12 mA II VI = VCC or GND VI = 0.
PAGE 704
SN74ALVCH162827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES013E – JULY 1995 – REVISED FEBRUARY 1999 operating characteristics, TA = 25°C PARAMETER Outputs enabled Power dissipation capacitance Cpd VCC = 1.8 V TYP † TEST CONDITIONS CL = 50 pF, Outputs disabled f = 10 MHz VCC = 2.5 V TYP VCC = 3.3 V TYP 16 18 4 6 † UNIT pF † This information was not available at the time of publication. PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 705
SN74ALVCH162827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES013E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 706
SN74ALVCH162827 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES013E – JULY 1995 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 707
SN74ALVCH162830 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES082F – AUGUST 1996 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D DBB PACKAGE (TOP VIEW) Widebus  Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JES
PAGE 708
SN74ALVCH162830 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES082F – AUGUST 1996 – REVISED FEBRUARY 1999 FUNCTION TABLE INPUTS OUTPUTS OE1 OE2 A 1Yn 2Yn L H H H Z L H L L Z H L H Z H H L L Z L L L H H H L L L L L H H X Z Z logic diagram (positive logic) OE2 OE1 21 20 5 A1 1Y1 7 4 2Y1 To 17 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . .
PAGE 709
SN74ALVCH162830 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES082F – AUGUST 1996 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC VCC VCC = 1.65 V VCC = 2.3 V –2 VCC = 2.7 V VCC = 3 V –8 –6 V V mA –12 VCC = 1.65 V VCC = 2.
PAGE 710
SN74ALVCH162830 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES082F – AUGUST 1996 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 4 mA IOL = 6 mA IOL = 8 mA IOL = 12 mA II VI = VCC or GND VI = 0.
PAGE 711
SN74ALVCH162830 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES082F – AUGUST 1996 – REVISED FEBRUARY 1999 operating characteristics, TA = 25°C PARAMETER All outputs enabled Power dissipation capacitance Cpd TEST CONDITIONS CL = 0, All outputs disabled VCC = 1.8 V TYP † f = 10 MHz VCC = 2.5 V TYP VCC = 3.3 V TYP 50 54 8 8 † UNIT pF † This information was not available at the time of publication. PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 712
SN74ALVCH162830 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES082F – AUGUST 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 713
SN74ALVCH162830 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS SCES082F – AUGUST 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 714
SN74ALVC162831 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCAS605A – APRIL 1998 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D DBB PACKAGE (TOP VIEW) Widebus  Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Pe
PAGE 715
SN74ALVC162831 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCAS605A – APRIL 1998 – REVISED FEBRUARY 1999 description (continued) The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
PAGE 716
SN74ALVC162831 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCAS605A – APRIL 1998 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
PAGE 717
SN74ALVC162831 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCAS605A – APRIL 1998 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA TYP† MAX 1.65 V VCC–0.2 1.2 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.
PAGE 718
SN74ALVC162831 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCAS605A – APRIL 1998 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER TO (OUTPUT) fmax VCC = 1.8 V MIN † A tpd Y CLK SEL ten tdis TYP VCC = 2.5 V ± 0.2 V MIN VCC = 2.7 V MAX 150 MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz † 1.1 4.7 4.8 1.5 4.3 † 1 5.3 5.3 1.4 4.
PAGE 719
SN74ALVC162831 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCAS605A – APRIL 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 720
SN74ALVC162831 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCAS605A – APRIL 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 721
SN74ALVC162831 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCAS605A – APRIL 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 1.5 V 0V 0V tsu th 2.7 V Data Input VOLTAGE WAVEFORMS PULSE DURATION 1.5 V 1.
PAGE 722
SN74ALVCH162831 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES084E – AUGUST 1996 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D DBB PACKAGE (TOP VIEW) Widebus  Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 m
PAGE 723
SN74ALVCH162831 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES084E – AUGUST 1996 – REVISED FEBRUARY 1999 description (continued) The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
PAGE 724
SN74ALVCH162831 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES084E – AUGUST 1996 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
PAGE 725
SN74ALVCH162831 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES084E – AUGUST 1996 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.
PAGE 726
SN74ALVCH162831 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES084E – AUGUST 1996 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER TO (OUTPUT) fmax VCC = 1.8 V MIN † A tpd Y CLK SEL ten tdis TYP VCC = 2.5 V ± 0.2 V MIN VCC = 2.7 V MAX 150 MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz † 1.1 4.7 4.8 1.5 4.3 † 1 5.3 5.3 1.4 4.
PAGE 727
SN74ALVCH162831 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES084E – AUGUST 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 728
SN74ALVCH162831 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES084E – AUGUST 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 729
SN74ALVCH162831 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCES084E – AUGUST 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V 0V 0V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.
PAGE 730
SN74ALVCH162832 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCAS588E – MAY 1997 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D DGG PACKAGE (TOP VIEW) Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA
PAGE 731
SN74ALVCH162832 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCAS588E – MAY 1997 – REVISED FEBRUARY 1999 description (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
PAGE 732
SN74ALVCH162832 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCAS588E – MAY 1997 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
PAGE 733
SN74ALVCH162832 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCAS588E – MAY 1997 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 4 mA IOL = 6 mA IOL = 8 mA IOL = 12 mA II VI = VCC or GND VI = 0.
PAGE 734
SN74ALVCH162832 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCAS588E – MAY 1997 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER TO (OUTPUT) fmax VCC = 1.8 V MIN † A tpd Y CLK SEL ten tdis VCC = 2.5 V ± 0.2 V TYP MIN MAX 150 VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz † 1.1 4.7 4.8 1.5 4.3 † 1 5.3 5.3 1.4 4.
PAGE 735
SN74ALVCH162832 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCAS588E – MAY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 736
SN74ALVCH162832 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCAS588E – MAY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 737
SN74ALVCH162832 1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS SCAS588E – MAY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 1.5 V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V Output Control (low-level enabling) 2.7 V 1.5 V 1.5 V 0V tPZL 2.
PAGE 738
SN74ALVC162834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES172A – DECEMBER 1998 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D Widebus  Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Outputs Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Pla
PAGE 739
SN74ALVC162834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES172A – DECEMBER 1998 – REVISED FEBRUARY 1999 FUNCTION TABLE INPUTS CLK A OUTPUT Y X X X Z L X L L L L X H H L H ↑ L L L H ↑ H L H H X H Y0† OE LE H L Y0‡ † Output level before the indicated steady-state input conditions were established, provided that CLK is high before LE goes high ‡ Output level before the indicated steady-state input conditions were established L H L X logic symbol§ OE CLK 27 EN1
PAGE 740
SN74ALVC162834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES172A – DECEMBER 1998 – REVISED FEBRUARY 1999 logic diagram (positive logic) OE CLK LE A1 27 30 28 54 1D C1 3 Y1 CLK To 17 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . .
PAGE 741
SN74ALVC162834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES172A – DECEMBER 1998 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC VCC VCC = 1.65 V VCC = 2.3 V –2 VCC = 2.7 V VCC = 3 V –8 –6 V V mA –12 VCC = 1.65 V VCC = 2.
PAGE 742
SN74ALVC162834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES172A – DECEMBER 1998 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA TYP† MAX 1.65 V VCC–0.2 1.2 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.
PAGE 743
SN74ALVC162834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES172A – DECEMBER 1998 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER VCC = 1.8 V TO (OUTPUT) MIN † fmax A tpd Y LE CLK ten tdis TYP VCC = 2.5 V ± 0.2 V MIN VCC = 2.7 V MAX 150 MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz † 1 5.2 5 1 4.2 † 1.3 6 6.8 1.3 5.8 † 1.4 6.
PAGE 744
SN74ALVC162834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES172A – DECEMBER 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 745
SN74ALVC162834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES172A – DECEMBER 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 746
SN74ALVC162834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES172A – DECEMBER 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V 500 Ω From Output Under Test S1 GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V 1.5 V 0V tPLH 1.
PAGE 747
SN74ALVC162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Ideal for Use in PC100 Register DIMM Revision 1.
PAGE 748
SN74ALVC162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999 FUNCTION TABLE INPUTS LE CLK A OUTPUT Y H X X X Z L H X L L L H X H H L L ↑ L L L L ↑ H H Y0† OE L L L or H X † Output level before the indicated steady-state input conditions were established logic symbol‡ OE CLK LE 27 EN1 30 2C3 28 C3 G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 3 1 1 3D 5 52 6 51 8 49 9 48 10 47 12 45 1
PAGE 749
SN74ALVC162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999 logic diagram (positive logic) OE CLK LE A1 27 30 28 54 1D C1 3 Y1 CLK To 17 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . .
PAGE 750
SN74ALVC162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC VCC VCC = 1.65 V VCC = 2.3 V –2 VCC = 2.7 V VCC = 3 V –8 –6 V V mA –12 VCC = 1.65 V VCC = 2.
PAGE 751
SN74ALVC162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA TYP† MAX 1.65 V VCC–0.2 1.2 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.
PAGE 752
SN74ALVC162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER TO (OUTPUT) fmax VCC = 1.8 V MIN † TYP Y LE CLK ten tdis MIN VCC = 2.7 V MAX 150 A tpd VCC = 2.5 V ± 0.2 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz † 1 5 5 1 4.2 † 1.3 5.9 5.8 1.3 5.1 † 1.4 6.
PAGE 753
SN74ALVC162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 754
SN74ALVC162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 755
SN74ALVC162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 756
SN74ALVC162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999 TYPICAL CHARACTERISTICS 0 ALVC162835 Pullup ǋ –0.01 x ) PC100 Requirements I OH – Output Current – mA –0.02 –0.03 –0.04 –0.05 –0.06 –0.07 –0.08 –0.09 –0.1 0.5 0 1.0 1.5 2.0 2.5 3.0 VOH – Output Voltage – V Figure 4. IV Characteristics – Pullup 0.12 ALVC162835 Pulldown x ) PC100 Requirements ǋ I OL – Output Current – mA 0.10 0.08 0.06 0.04 0.02 0.00 0 0.5 1.0 1.5 2.
PAGE 757
SN74ALVCH162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES121D – JULY 1997 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Output Port Has Equivalent 26-Ω Series Resistors, So No External Resistors Are Required ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA P
PAGE 758
SN74ALVCH162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES121D – JULY 1997 – REVISED FEBRUARY 1999 FUNCTION TABLE INPUTS LE CLK A OUTPUT Y H X X X Z L H X L L L H X H H L L ↑ L L L L ↑ H H Y0† OE L L L or H X † Output level before the indicated steady-state input conditions were established logic symbol‡ OE CLK LE 27 EN1 30 2C3 28 C3 G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 3 1 5 1 3D 52 6 51 8 49 9 48 10 47 12 45 13
PAGE 759
SN74ALVCH162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES121D – JULY 1997 – REVISED FEBRUARY 1999 logic diagram (positive logic) OE CLK LE A1 27 30 28 54 1D C1 3 Y1 CLK To 17 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . .
PAGE 760
SN74ALVCH162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES121D – JULY 1997 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC VCC VCC = 1.65 V VCC = 2.3 V –2 VCC = 2.7 V VCC = 3 V –8 –6 V V mA –12 VCC = 1.65 V VCC = 2.
PAGE 761
SN74ALVCH162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES121D – JULY 1997 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 4 mA IOL = 6 mA IOL = 8 mA IOL = 12 mA II VI = VCC or GND VI = 0.
PAGE 762
SN74ALVCH162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES121D – JULY 1997 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw tsu Clock frequency Pulse duration Setup time MIN MAX MIN 150 MAX VCC = 3.3 V ± 0.3 V MIN 150 3.3 3.3 3.3 CLK high or low † 3.3 3.3 3.3 Data before CLK↑ † 2.2 2.1 1.7 CLK high † 1.9 1.6 1.5 CLK low † 1.3 1.1 1 † 0.
PAGE 763
SN74ALVCH162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES121D – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 764
SN74ALVCH162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES121D – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 765
SN74ALVCH162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES121D – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 766
SN74ALVC162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES129B – MARCH 1998 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Output Port Has Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink
PAGE 767
SN74ALVC162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES129B – MARCH 1998 – REVISED FEBRUARY 1999 FUNCTION TABLE INPUTS CLK A OUTPUT Y X X X Z L X L L L L X H H L H ↑ L L L H ↑ H H Y0† OE LE H L L H L or H X † Output level before the indicated steady-state input conditions were established logic symbol‡ OE CLK LE 1 EN1 56 29 2C3 C3 G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 2 1 1 3D 3 54 5 52 6 51 1 8 49 9 48 10
PAGE 768
SN74ALVC162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES129B – MARCH 1998 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1 OE 56 CLK LE 29 55 A1 1D C1 2 Y1 CLK To 19 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . .
PAGE 769
SN74ALVC162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES129B – MARCH 1998 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC VCC VCC = 1.65 V VCC = 2.3 V –2 VCC = 2.7 V VCC = 3 V –8 –6 V V mA –12 VCC = 1.65 V VCC = 2.
PAGE 770
SN74ALVC162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES129B – MARCH 1998 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA TYP† MAX 1.65 V VCC–0.2 1.2 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.
PAGE 771
SN74ALVC162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES129B – MARCH 1998 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER TO (OUTPUT) fmax VCC = 1.8 V MIN † A tpd Y LE CLK ten tdis VCC = 2.5 V ± 0.2 V TYP MIN VCC = 2.7 V MAX 150 MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz † 1 4.4 4.6 1.2 4 † 1.1 5.8 6.1 1.4 5.1 † 1 5.
PAGE 772
SN74ALVC162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES129B – MARCH 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 773
SN74ALVC162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES129B – MARCH 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 774
SN74ALVC162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES129B – MARCH 1998 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 775
SN74ALVCH162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES122D – JULY 1997 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Output Port Has Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Designed to Comply With JEDEC 168-Pin and 200-Pin SDRAM Buffered DIMM Specification ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Excee
PAGE 776
SN74ALVCH162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES122D – JULY 1997 – REVISED FEBRUARY 1999 FUNCTION TABLE INPUTS CLK A OUTPUT Y X X X Z L X L L L L X H H L H ↑ L L L H ↑ H H Y0† OE LE H L L H L or H X † Output level before the indicated steady-state input conditions were established logic symbol‡ OE CLK LE 1 EN1 56 29 2C3 C3 G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 2 1 1 3D 3 54 5 52 6 51 1 8 49 9 48 10
PAGE 777
SN74ALVCH162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES122D – JULY 1997 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1 OE 56 CLK LE 29 55 A1 1D C1 2 Y1 CLK To 19 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . .
PAGE 778
SN74ALVCH162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES122D – JULY 1997 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC VCC VCC = 1.65 V VCC = 2.3 V –2 VCC = 2.7 V VCC = 3 V –8 –6 V V mA –12 VCC = 1.65 V VCC = 2.
PAGE 779
SN74ALVCH162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES122D – JULY 1997 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 4 mA IOL = 6 mA IOL = 8 mA IOL = 12 mA II VI = VCC or GND VI = 0.
PAGE 780
SN74ALVCH162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES122D – JULY 1997 – REVISED FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw tsu Clock frequency Pulse duration Setup time MIN MAX MIN 150 MAX VCC = 3.3 V ± 0.3 V MIN 150 LE low 3.3 3.3 3.3 † 3.3 3.3 3.3 Data before CLK↑ † 1.4 1.7 1.5 CLK high † 1.2 1.6 1.3 CLK low † 1.4 1.5 1.2 † 0.9 0.
PAGE 781
SN74ALVCH162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES122D – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 782
SN74ALVCH162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES122D – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 783
SN74ALVCH162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCES122D – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 784
SN74ALVCH162841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES088C – OCTOBER 1996 – REVISED FEBRUARY 1999 D Member of the Texas Instruments D D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 25
PAGE 785
SN74ALVCH162841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES088C – OCTOBER 1996 – REVISED FEBRUARY 1999 description (continued) Active bus-hold circuitry is provided to hold unused or floating inputs at a valid logic level. The SN74ALVCH162841 is characterized for operation from –40°C to 85°C.
PAGE 786
SN74ALVCH162841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES088C – OCTOBER 1996 – REVISED FEBRUARY 1999 logic diagram (positive logic) 1OE 1LE 1 2OE 56 2LE C1 1D1 55 2 1D 28 29 C1 1Q1 2D1 42 To Nine Other Channels 1D 15 2Q1 To Nine Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 787
SN74ALVCH162841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES088C – OCTOBER 1996 – REVISED FEBRUARY 1999 recommended operating conditions (see Note 4) VCC VIH Supply voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V High-level input voltage VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL Low-level input voltage VI VO Input voltage IOH IOL ∆t/∆v MIN MAX 1.65 3.6 2 0.35 × VCC 0.7 VCC VCC VCC = 1.65 V VCC = 2.3 V –2 VCC = 2.7 V VCC = 3 V –8 –6 V V mA –12 VCC = 1.
PAGE 788
SN74ALVCH162841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES088C – OCTOBER 1996 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –2 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 2 mA 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 4 mA IOL = 6 mA IOL = 8 mA IOL = 12 mA II VI = VCC or GND VI = 0.
PAGE 789
SN74ALVCH162841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES088C – OCTOBER 1996 – REVISED FEBRUARY 1999 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER TO (OUTPUT) D tpd Q LE ten VCC = 1.8 V Q OE tdis Q OE † This information was not available at the time of publication. VCC = 2.5 V ± 0.2 V TYP † MIN MAX 1 † VCC = 2.7 V MIN VCC = 3.3 V ± 0.3 V UNIT MAX MIN MAX 5.
PAGE 790
SN74ALVCH162841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES088C – OCTOBER 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 791
SN74ALVCH162841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES088C – OCTOBER 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 792
SN74ALVCH162841 20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS SCES088C – OCTOBER 1996 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V From Output Under Test 6V Open S1 500 Ω GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.
PAGE 793
General Information ALVC Gates/Octals ALVC Widebus/Widebus+ ALVC Widebus With Series Damping Resistors ALVC Dual-Supply-Voltage Translators SSTL HSTL ALB Mechanical Data A Output Derating Curves 5–1
PAGE 794
Contents Page SN74ALVC164245 ALVC Dual-Supply-Voltage Translators 5–2 16-Bit 3.3-V to 5-V Level Shifting Transceiver With 3-State Outputs . . . . . . . . . . . . . .
PAGE 795
SN74ALVC164245 16-BIT 3.
PAGE 796
SN74ALVC164245 16-BIT 3.
PAGE 797
SN74ALVC164245 16-BIT 3.3-V TO 5-V LEVEL SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS416F – MARCH 1994 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range for VCCB at 5 V and VCCA at 3.3 V (unless otherwise noted)† Supply voltage range: VCCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V VCCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 798
SN74ALVC164245 16-BIT 3.3-V TO 5-V LEVEL SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS416F – MARCH 1994 – REVISED FEBRUARY 1999 recommended operating conditions for VCCA at 3.3 V (see Note 4) MIN MAX 2.7 3.6 VCCA VIH Supply voltage VIL VIB Low-level input voltage Input voltage 0 VOA Output voltage 0 High-level input voltage VCCA = 2.7 V to 3.6 V VCCA = 2.7 V to 3.6 V IOH High-level output current VCCA = 2.7 V VCCA = 3 V IOL Low-level output current VCCA = 2.
PAGE 799
SN74ALVC164245 16-BIT 3.3-V TO 5-V LEVEL SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS416F – MARCH 1994 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range for VCCA = 3.3 V (unless otherwise noted) (see Note 6) PARAMETER TEST CONDITIONS VCCA 2.7 V to 3.6 V IOH = –100 µA VOH (B to A) 2.7 V IOH = –12 mA IOH = –24 mA IOL = 100 µA VOL (B to A) II IOZ‡ Control inputs ICC ∆ICC§ Ci TYP† MAX VCC–0.2 2.2 3V 2.4 3V 2 UNIT V 2.7 V to 3.6 V 0.
PAGE 800
SN74ALVC164245 16-BIT 3.3-V TO 5-V LEVEL SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS416F – MARCH 1994 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCCA = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND 3V Output Control (low-level enabling) LOAD CIRCUIT 1.5 V 0V tPLZ tPZL 3V Input 1.5 V 1.5 V 0V tPLH 1.5 V ≈3V 1.5 V 1.
PAGE 801
SN74ALVC164245 16-BIT 3.3-V TO 5-V LEVEL SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS416F – MARCH 1994 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCCB = 5 V ± 0.5 V 2 S1 500 Ω From Output Under Test CL = 50 pF (see Note A) VCCB Open GND 500 Ω S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 VCCB GND 2.7 V Output Control (low-level enabling) LOAD CIRCUIT TEST 1.5 V 0V tPLZ tPZL 2.7 V Input 1.5 V 1.
PAGE 802
General Information ALVC Gates/Octals ALVC Widebus/Widebus+ ALVC Widebus With Series Damping Resistors ALVC Dual-Supply-Voltage Translators SSTL HSTL ALB Mechanical Data A Output Derating Curves 6–1
PAGE 803
Contents Page SN74SSTL16837A SN74SSTL16847 SN74SSTL16857 SN74SSTL32867 SN74SSTL32877 SSTL 6–2 20-Bit SSTL_3 Interface Universal Bus Driver With 3-State Outputs . . . . . . . . . . . . . . 20-Bit SSTL_3 Interface Buffer With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-Bit SSTL_2 Registered Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-Bit Registered Buffer With SSTL_2 Inputs and LVCMOS Outputs . . . . . . . . . . . . . .
PAGE 804
SN74SSTL16837A 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998 D Member of the Texas Instruments D D D D D DGG PACKAGE (TOP VIEW) Widebus Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB Layout Meets SSTL_3 Class I and Class II Specifications Latch-Up Performance Exceeds 250 mA Per JESD 17 Packaged in Plastic Thin Shrink Small-Outline Package Y1 Y2 GND Y3 Y4 VDDQ Y5 Y6 GND Y7 Y8 VDDQ Y9 Y10 GND
PAGE 805
SN74SSTL16837A 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998 FUNCTION TABLE INPUTS OE LE CLK A OUTPUT Y L H X H H L H X L L L L ↑ H H L L ↑ L L L L H X Y0† Y0‡ L L L X H X X X Z † Output level before the indicated steady-state input conditions were established, provided that CLK was high before LE went low ‡ Output level before the indicated steady-state input conditions were established logic diag
PAGE 806
SN74SSTL16837A 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998 recommended operating conditions (see Note 4) MIN VCC VDDQ Supply voltage VREF VTT Reference voltage (VREF = 0.
PAGE 807
SN74SSTL16837A 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 3.3 V ± 0.3 V MIN fclock Clock frequency tw Pulse duration 200 LE high 2.5 CLK high or low 2.5 A before CLK↑ tsu th Setup time A before LE↓ ↓ A after CLK↑ Hold time A after LE↓ LE low 1.5 CLK high 1.
PAGE 808
SN74SSTL16837A 20-BIT SSTL_3 INTERFACE UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS675G – SEPTEMBER 1996 – REVISED SEPTEMBER 1998 PARAMETER MEASUREMENT INFORMATION VTT Test Point 25 Ω 25 Ω = SSTL_3 Class II 50 Ω = SSTL_3 Class I CL = 10 pF or 30 pF (see Note A) LOAD CIRCUIT 1.9 V tw 1.5 V Timing Input 1.9 V 1.1 V 1.5 V Input tsu 1.1 V 1.9 V Data Input 1.5 V th 1.5 V VOLTAGE WAVEFORMS PULSE DURATION 1.5 V 1.1 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.9 V Output Control 1.5 V 1.
PAGE 809
SN74SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A – OCTOBER 1997 – REVISED MAY 1998 D Member of the Texas Instruments D D D D D D DGG PACKAGE (TOP VIEW) Widebus Family Supports SSTL_3 Signal Inputs and Outputs Flow-Through Architecture Optimizes PCB Layout Meets SSTL_3 Class I and Class II Specifications ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Packaged in Pla
PAGE 810
SN74SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A – OCTOBER 1997 – REVISED MAY 1998 FUNCTION TABLE INPUTS OE A OUTPUT Y L H H L L L H X Z logic diagram (positive logic) OE A1 16 1 64 Y1 To 19 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.
PAGE 811
SN74SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A – OCTOBER 1997 – REVISED MAY 1998 recommended operating conditions (see Note 4) MIN VCC VDDQ Supply voltage VREF VTT Reference voltage (VREF = 0.
PAGE 812
SN74SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A – OCTOBER 1997 – REVISED MAY 1998 switching characteristics over recommended operating free-air temperature range, Class I, VREF = VTT = VDDQ X 0.45 and CL = 10 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX tpd A Y 1.5 3 ns ten OE Y 1.5 4 ns tdis OE Y 1.6 4.
PAGE 813
SN74SSTL16847 20-BIT SSTL_3 INTERFACE BUFFER WITH 3-STATE OUTPUTS SCBS709A – OCTOBER 1997 – REVISED MAY 1998 PARAMETER MEASUREMENT INFORMATION VTT Test Point 25 Ω = SSTL_3 Class II 50 Ω = SSTL_3 Class I 25 Ω CL = 10 pF or 30 pF (see Note A) LOAD CIRCUIT Timing Input VIH‡ VREF† tsu tw VIL§ VIH‡ VREF† VREF† Input th VIL§ VIH‡ Data Input VREF† VREF† VOLTAGE WAVEFORMS PULSE DURATION VIL§ VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control VIL§ tPLH Output VREF† VIL§ tPLZ Output Wa
PAGE 814
SN74SSTL16857 14-BIT SSTL_2 REGISTERED BUFFER SCAS625 – FEBRUARY 1999 D Member of the Texas Instruments D D D D D Widebus Family Supports SSTL_2 Signal Data Inputs and Outputs Supports LVTTL Switching Levels on the RESET Pin Differential CLK Signal Flow-Through Architecture Optimizes PCB Layout Meets SSTL_2 Class I and Class II Specifications Packaged in Plastic Thin Shrink Small-Outline Package Q1 Q2 GND VDDQ Q3 Q4 Q5 GND VDDQ Q6 Q7 VDDQ GND Q8 Q9 VDDQ GND Q10 Q11 Q12 VDDQ GND Q13 Q14 description Thi
PAGE 815
SN74SSTL16857 14-BIT SSTL_2 REGISTERED BUFFER SCAS625 – FEBRUARY 1999 FUNCTION TABLE (each flip-flop) INPUTS RESET CLK CLK D OUTPUT Q L X X X L H ↓ ↑ H H H ↓ ↑ L L H L or H L or H X Q0 logic diagram (positive logic) RESET CLK CLK PRODUCT PREVIEW VREF D1 34 38 39 35 48 1D C1 1 Q1 R To 13 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC or VDDQ . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 816
SN74SSTL16857 14-BIT SSTL_2 REGISTERED BUFFER SCAS625 – FEBRUARY 1999 recommended operating conditions (see Note 4) NOM VDDQ 2.
PAGE 817
SN74SSTL16857 14-BIT SSTL_2 REGISTERED BUFFER SCAS625 – FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK II = – 18 mA IOH = – 100 µA VOH IOH = – 8 mA IOH = – 16 mA PRODUCT PREVIEW CLK, CLK 2.7 V VI = 2.7 V or 0 VI = 1.7 V or 0.8V VREF = 1.15 V or 1.35 V 3.6 V 2.7 V VI = 2.7 V or 0 VI = 1.7 V or 0.8V VREF = 1.15 V or 1.35 V 3.6 V VI = 2.7 V or 0 RESET VI = VCC or GND VREF VREF = 1.15 V or 1.
PAGE 818
SN74SSTL16857 14-BIT SSTL_2 REGISTERED BUFFER SCAS625 – FEBRUARY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V ± 0.2 V MIN fclock tw MAX VCC = 3.3 V ± 0.
PAGE 819
SN74SSTL16857 14-BIT SSTL_2 REGISTERED BUFFER SCAS625 – FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V AND VCC = 3.3 V ± 0.
PAGE 820
SN74SSTL32867 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS DESIGN GOAL DESIGN GOAL SCES240A – APRIL 1999 – REVISED MAY 1999 D Member of the Texas Instruments D D D D Differential CLK Signal D Advanced ULTTL Output Circuitry Widebus Family Supports SSTL_2 Signal Data Inputs Supports LVTTL Switching Levels on the RESET Pin Flow-Through Architecture Optimizes PCB Layout D Eliminates Switching Noise in Unterminated Line Packaged in Plastic Fine-Pitch Ball-Grid-Array Package descriptio
PAGE 821
SN74SSTL32867 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS DESIGN GOAL SCES240A – APRIL 1999 – REVISED MAY 1999 FUNCTION TABLE INPUTS CLK A OUTPUT Y ↑ ↓ H H ↑ ↓ L L H L or H L or H X Y0 L X X X L RESET CLK H H logic diagram (positive logic) RESET CLK CLK PRODUCT PREVIEW VREF A1 K2 J1 K1 B3 A1 1D C1 A5 Y1 R To 25 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC or VDDQ . .
PAGE 822
SN74SSTL32867 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS DESIGN GOAL SCES240A – APRIL 1999 – REVISED MAY 1999 recommended operating conditions (see Note 4) NOM MAX VCC VDDQ Supply voltage VDDQ 2.
PAGE 823
SN74SSTL32867 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS DESIGN GOAL SCES240A – APRIL 1999 – REVISED MAY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V ± 0.2 V MIN TYP MAX fclock tw Clock frequency 200 Pulse duration, CLK, CLK high or low 1.6 0.8 Data before CLK↑, CLK↓ 1.1 0.5 RESET high before CLK↑, CLK↓ 1.1 0.5 0.
PAGE 824
SN74SSTL32867 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS DESIGN GOAL SCES240A – APRIL 1999 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 825
SN74SSTL32877 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS DESIGN GOAL DESIGN GOAL SCES241A – APRIL 1999 – REVISED MAY 1999 D Member of the Texas Instruments D D D D Differential CLK Signal D Meets SSTL_2 Class I and Class II Widebus Family Supports SSTL_2 Signal Data Inputs and Outputs Supports LVTTL Switching Levels on the RESET Pin Flow-Through Architecture Optimizes PCB Layout Specifications D Packaged in Plastic Fine-Pitch Ball-Grid-Array Package description This 26-bit registered b
PAGE 826
SN74SSTL32877 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS DESIGN GOAL SCES241A – APRIL 1999 – REVISED MAY 1999 FUNCTION TABLE INPUTS OE RESET L H L H CLK A OUTPUT Y ↑ ↓ H H ↑ ↓ L L CLK L H L or H L or H X Yo H H X X X Z X L X X X L logic diagram (positive logic) RESET CLK CLK PRODUCT PREVIEW OE VREF A1 K2 J1 K1 R3 B3 A1 1D C1 A5 Y1 R To 25 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Sup
PAGE 827
SN74SSTL32877 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS DESIGN GOAL SCES241A – APRIL 1999 – REVISED MAY 1999 recommended operating conditions (see Note 4) NOM MAX VCC VDDQ Supply voltage VDDQ 2.
PAGE 828
SN74SSTL32877 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS DESIGN GOAL SCES241A – APRIL 1999 – REVISED MAY 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V ± 0.2 V MIN TYP MAX fclock tw Clock frequency 200 Pulse duration, CLK, CLK high or low 1.6 0.8 Data before CLK↑, CLK↓ 1.1 0.5 RESET high before CLK↑, CLK↓ 1.1 0.5 0.
PAGE 829
SN74SSTL32877 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS DESIGN GOAL SCES241A – APRIL 1999 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 830
General Information ALVC Gates/Octals ALVC Widebus/Widebus+ ALVC Widebus With Series Damping Resistors ALVC Dual-Supply-Voltage Translators SSTL HSTL ALB Mechanical Data A Output Derating Curves 7–1
PAGE 831
Contents Page SN74HSTL16918 SN74HSTL162822 HSTL 7–2 9-Bit to 18-Bit HSTL-to-LVTTL Memory Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3 14-Bit to 28-Bit HSTL-to-LVTTL Memory Address Latch . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 832
SN74HSTL16918 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES096C – APRIL 1997 – REVISED JANUARY 1999 D Member of the Texas Instruments D D D D DGG PACKAGE (TOP VIEW) Widebus Family Inputs Meet JEDEC HSTL Std JESD 8-6 and Outputs Meet Level III Specifications ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Packaged in Plastic Thin Shrink Small-Outline Package 2Q1 1Q1 GND D1 D2 VCC D
PAGE 833
SN74HSTL16918 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES096C – APRIL 1997 – REVISED JANUARY 1999 logic diagram (positive logic) 10 1LE 4 D1 1D 2 1Q1 C1 14 1D 2LE 1 2Q1 C1 To Eight Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . .
PAGE 834
SN74HSTL16918 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES096C – APRIL 1997 – REVISED JANUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VOH VCC = 3.15 V, VCC = 3.15 V, II = –18 mA IOH = –24 mA VOL VCC = 3.15 V, IOL = 24 mA VI = 0 or 1.5 V Control inputs II Data inputs VCC = 3.45 V Ci Control inputs Data inputs TYP† UNIT –1.2 V V 0.5 V ±5 ±5 µA 90 VCC = 3.45 V, VCC = 0 or 3.
PAGE 835
SN74HSTL16918 9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES096C – APRIL 1997 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION 1.25 V VREF LE From Output Under Test 0.25 V CL = 80 pF (see Note A) tsu 500 Ω th 1.25 V Data Input VREF VREF 0.25 V LOAD CIRCUIT VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input (see Note B) 1.25 V VREF VREF 0.25 V tPLH tw tPHL 1.25 V Input VREF VREF VOH Output 1.5 V 0.25 V VOL VOLTAGE WAVEFORMS PULSE DURATION NOTES: A. B. C. D.
PAGE 836
SN74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 D Member of the Texas Instruments D D D DGG PACKAGE (TOP VIEW) Widebus Family Inputs Meet JEDEC HSTL Standard JESD8-6 All Outputs Have Equivalent 25-Ω Series Resistors Packaged in Plastic Thin Shrink Small-Outline Package 1Q2 2Q1 1Q1 GND D1 D2 D3 VCC D4 D5 D6 GND D7 1LE VCC VREF GND GND 2LE D8 GND D9 D10 D11 VCC D12 D13 D14 GND 1Q14 2Q14 1Q13 description This 14-bit to 28-bit D-type latch i
PAGE 837
SN74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 logic diagram (positive logic) 14 1LE 5 D1 1D 3 1Q1 C1 19 1D 2LE 2 2Q1 C1 To 13 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . .
PAGE 838
SN74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VOH VCC = 3.15 V, VCC = 3.15 V, II = –18 mA IOH = –12 mA VOL VCC = 3.15 V, IOL = 12 mA VI = 0 or 1.5 V Control inputs II Data inputs VCC = 3.45 V Ci Control inputs Data inputs TYP† UNIT –1.2 V V 0.8 V 5 5 µA 90 VCC = 3.45 V, VCC = 0 or 3.
PAGE 839
SN74HSTL162822 14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH SCES091A – DECEMBER 1996 – REVISED APRIL 1997 PARAMETER MEASUREMENT INFORMATION 1.25 V VREF LE From Output Under Test 0.25 V CL = 80 pF (see Note A) tsu 500 Ω th 1.25 V Data Input VREF VREF 0.25 V LOAD CIRCUIT VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input (see Note B) 1.25 V VREF VREF 0.25 V tPLH tw tPHL 1.25 V Input VREF VREF VOH Output 1.5 V 0.25 V VOL VOLTAGE WAVEFORMS PULSE DURATION NOTES: A. B. C. D.
PAGE 840
General Information ALVC Gates/Octals ALVC Widebus/Widebus+ ALVC Widebus With Series Damping Resistors ALVC Dual-Supply-Voltage Translators SSTL HSTL ALB Mechanical Data A Output Derating Curves 8–1
PAGE 841
Contents Page SN74ALB16244 SN74ALB16245 ALB 8–2 16-Bit Buffer/Driver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3 3.3-V ALB 16-Bit Transceiver With 3-State Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 842
SN74ALB16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCBS647C – AUGUST 1995 – REVISED JULY 1997 D Member of the Texas Instruments D D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family State-of-the-Art Advanced Low-Voltage BiCMOS (ALB) Technology Design for 3.
PAGE 843
SN74ALB16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCBS647C – AUGUST 1995 – REVISED JULY 1997 logic symbol† 1OE 2OE 1 EN1 48 25 3OE 4OE 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 24 EN2 EN3 EN4 47 1 1 46 3 44 5 43 6 41 40 1 2 8 9 38 11 37 12 36 13 35 1 3 14 33 16 32 17 30 1 4 19 29 20 27 22 26 23 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PAGE 844
SN74ALB16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCBS647C – AUGUST 1995 – REVISED JULY 1997 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 1 3OE 47 2 46 3 44 5 43 6 1Y1 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 48 4OE 41 8 40 9 38 11 37 12 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 25 36 13 35 14 33 16 32 17 3Y1 3Y2 3Y3 3Y4 24 30 19 29 20 27 22 26 23 4Y1 4Y2 4Y3 4Y4 absolute maximum ratings over operating free-air temperature rang
PAGE 845
SN74ALB16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCBS647C – AUGUST 1995 – REVISED JULY 1997 recommended operating conditions MIN 3 MAX UNIT VCC IOH† Supply voltage 3.6 V High-level output current –25 mA IOL† ∆t/∆v Low-level output current 25 mA 5 ns/V 85 °C Input transition rise or fall rate Outputs enabled TA Operating free-air temperature † Refer to Figures 1 and 2 for typical I/O ranges.
PAGE 846
SN74ALB16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCBS647C – AUGUST 1995 – REVISED JULY 1997 OUTPUT VOLTAGE HIGH vs INPUT VOLTAGE VOH – Output Voltage – V 3.5 3 2.5 –100 µA –25 mA –6 mA 2 1.5 1.5 2 2.5 3 3.5 4 VI – Input Voltage – V Figure 1. VOH Over Recommended Free-Air Temperature Range OUTPUT VOLTAGE LOW vs INPUT VOLTAGE 2 VOL – Output Voltage – V 1.5 25 mA 1 100 µA 0.5 6 mA 0 0 0.5 1 1.5 2 VI – Input Voltage – V Figure 2.
PAGE 847
SN74ALB16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCBS647C – AUGUST 1995 – REVISED JULY 1997 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 3V Input 3V Timing Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 3V Data Input 1.5 V 1.5 V 0V 3V Output Control (low-level enabling) VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 1.5 V 0V tPZL 3V 1.
PAGE 848
SN74ALB16245 3.3-V ALB 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS SCBS678B – SEPTEMBER 1996 – REVISED JULY 1997 D Member of the Texas Instruments D D D D D D DGG OR DL PACKAGE (TOP VIEW) Widebus  Family State-of-the-Art Advanced Low-Voltage BiCMOS (ALB) Technology Design for 3.
PAGE 849
SN74ALB16245 3.
PAGE 850
SN74ALB16245 3.3-V ALB 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS SCBS678B – SEPTEMBER 1996 – REVISED JULY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.
PAGE 851
SN74ALB16245 3.3-V ALB 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS SCBS678B – SEPTEMBER 1996 – REVISED JULY 1997 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 3) VCC = 3.3 V ± 0.3 V MIN TYP† MAX PARAMETER FROM (INPUT) TO (OUTPUT) tpd A or B B or A 0.6 1.3 2 ns ten OE A or B 1.5 3.2 6 ns tdis OE † All typical values are at VCC = 3.3 V, TA = 25°C. A or B 1.8 2.8 4.
PAGE 852
SN74ALB16245 3.3-V ALB 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS SCBS678B – SEPTEMBER 1996 – REVISED JULY 1997 OUTPUT VOLTAGE HIGH vs INPUT VOLTAGE VOH – Output Voltage – V 3.5 3 2.5 –100 µA –25 mA –6 mA 2 1.5 1.5 2 2.5 3 3.5 4 VI – Input Voltage – V Figure 1. VOH Over Recommended Free-Air Temperature Range OUTPUT VOLTAGE LOW vs INPUT VOLTAGE 2 VOL – Output Voltage – V 1.5 25 mA 1 100 µA 0.5 6 mA 0 0 0.5 1 1.5 2 VI – Input Voltage – V Figure 2.
PAGE 853
SN74ALB16245 3.3-V ALB 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS SCBS678B – SEPTEMBER 1996 – REVISED JULY 1997 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 3V Input 3V Timing Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 3V Data Input 1.5 V 1.5 V 0V 3V Output Control (low-level enabling) VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 1.5 V 0V tPZL 3V 1.
PAGE 854
General Information ALVC Gates/Octals ALVC Widebus/Widebus+ ALVC Widebus With Series Damping Resistors ALVC Dual-Supply-Voltage Translators SSTL HSTL ALB Mechanical Data A Output Derating Curves 9–1
PAGE 855
Contents Page Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–3 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–5 D (R-PDSO-G**) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 856
ORDERING INSTRUCTIONS Electrical characteristics presented in this data book, unless otherwise noted, apply for the circuit type(s) listed in the page heading regardless of package. The availability of a circuit function in a particular package is denoted by an alphabetical reference above the pin-connection diagram(s). These alphabetical references refer to mechanical outline drawings shown in this section.
PAGE 857
MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN PINS ** 0.050 (1,27) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.244 (6,20) 0.228 (5,80) 0.008 (0,20) NOM 0.157 (4,00) 0.150 (3,81) 1 Gage Plane 7 A 0.010 (0,25) 0°–ā8° 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) 4040047 / D 10/96 NOTES: A. B. C. D.
PAGE 858
MECHANICAL DATA DBB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 80 PIN SHOWN 0,23 0,13 0,40 80 0,07 M 41 6,20 6,00 8,40 7,80 0,16 NOM 1 Gage Plane 40 A 0,25 0°–ā12° 0,75 0,50 Seating Plane 1,20 MAX 0,08 0,15 PINS** 80 100 A MAX 17,10 20,90 A MIN 16,90 20,70 DIM 4040212 / D 03/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. The 80-pin falls within JEDEC MO-153 and the 100-pin falls within JEDEC MO-194.
PAGE 859
MECHANICAL DATA DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PIN SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°–ā8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15.
PAGE 860
MECHANICAL DATA DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 24 PIN SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–ā8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 48 56 A MAX 3,70 3,70 5,10 5,10 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 9,60 11,20 DIM 4073251/b 03/97 NOTES: A. B. C. D. 9–8 All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 861
MECHANICAL DATA DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48-PIN SHOWN 0.025 (0,635) 0.012 (0,305) 0.008 (0,203) 48 0.005 (0,13) M 25 0.006 (0,15) NOM 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / D 08/97 NOTES: A. B.
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MECHANICAL DATA DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 16 0.010 (0,25) M 9 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.293 (7,45) Gage Plane 0.010 (0,25) 1 8 0°–ā8° A 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS ** 0.004 (0,10) 16 20 24 28 A MAX 0.410 (10,41) 0.510 (12,95) 0.610 (15,49) 0.710 (18,03) A MIN 0.400 (10,16) 0.500 (12,70) 0.600 (15,24) 0.
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MECHANICAL DATA GKE (R-PBGA-N96) PLASTIC BALL GRID ARRAY 5,60 5,40 4,00 TYP 0,80 0,40 12,00 TYP 0,40 13,60 13,40 0,80 T R P N M L K J H G F E D C B A 1 2 3 4 5 6 0,95 0,85 1,40 MAX Seating Plane 0,55 0,45 0,08 M 0,45 0,35 0,10 4188953/A 10/98 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar BGA configuration MicroStar BGA is a trademark of Texas Instruments Incorporated.
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MECHANICAL DATA GKF (R-PBGA-N114) PLASTIC BALL GRID ARRAY 4,00 TYP 5,60 5,40 0,80 0,40 16,10 15,90 0,80 W V U T R P N M L K J H G F E D C B A 14,40 TYP 1 2 3 4 5 6 0,95 0,85 1,40 MAX Seating Plane 0,55 0,45 0,08 M 0,45 0,35 0,10 4188954/A 10/98 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar BGA configuration MicroStar BGA is a trademark of Texas Instruments Incorporated.
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MECHANICAL DATA NS (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0,51 0,35 1,27 14 0,25 M 8 0,15 NOM 5,60 5,00 8,20 7,40 Gage Plane 1 7 0,25 0°–ā10° A 1,05 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 A MAX 10,50 10,50 12,90 15,30 A MIN 9,90 9,90 12,30 14,70 DIM 4040062 / B 02/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°–ā8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. 9–14 All linear dimensions are in millimeters. This drawing is subject to change without notice.
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General Information ALVC Gates/Octals ALVC Widebus/Widebus+ ALVC Widebus With Series Damping Resistors ALVC Dual-Supply-Voltage Translators SSTL HSTL ALB Mechanical Data A Output Derating Curves A–1
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A Output Derating Curves A–2
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Output Derating Curves Propagation-delay, enable-time, and disable-time parameter values in the ALVC data sheets are provided with VCC ranging from 3 V to 3.6 V and with a load capacitance of 50 pF. As the load capacitance varies, values for these parameters change. Data for Figures 1 through 3 were taken under worst-case scenarios, i.e., with VCC at 3 V and TA = 85°C. The data are for capacitive loads from 10 pF to 50 pF, in 10-pF increments.
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Figure A–2 illustrates the effect of load capacitance on disable time for high-to-3-state and low-to-3-state transitions for OE to A and OE to B, respectively. High-to-3-state and low-to-3-state for OE to B and OE to A results, respectively, were slightly faster, but for clarity are not illustrated. For disable time, a 10-pF decrease in load capacitance produces approximately a 14% decrease in disable time. DISABLE TIME vs LOAD CAPACITANCE 3.5 OE to A tPHZ OE to B tPLZ t dis – Disable Time – ns 3.0 2.
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Figure A–3 illustrates the effect of load capacitance on enable time for 3-state-to-high and 3-state-to-low transitions for OE to A and OE to B, respectively. 3-state-to-high and 3-state-to-low for OE to B and OE to A results, respectively, were slightly faster, but for clarity are not illustrated. For enable time, a 10-pF decrease in load capacitance produces approximately a 10% decrease in enable time. ENABLE TIME vs LOAD CAPACITANCE 3.5 OE to A tPZH OE to B tPZL t en – Enable Time – ns 3.0 2.5 2.
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A–6