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FEATURES

DGV, DW, OR PW PACKAGE

(TOP VIEW)

GND

DESCRIPTION/ORDERING INFORMATION

SN74ALVCH373

OCTAL TRANSPARENT D-TYPE LATCH

WITH 3-STATE OUTPUTS

SCES116H – JULY 1997 – REVISED OCTOBER 2004

• Operates From 1.65 V to 3.6 V

• Max t

of 3.3 ns at 3.3 V

• ± 24-mA Output Drive at 3.3 V

• Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

This octal transparent D-type latch is designed for 1.65-V to 3.6-V V

operation.

The SN74ALVCH373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers,

and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When

LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

A buffered output-enable ( OE) input can be used to place the eight outputs in either a normal logic state (high or

low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the

bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines

without interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

Tube SN74ALVCH373DW

SOIC - DW ALVCH373

Tape and reel SN74ALVCH373DWR

TSSOP - PW Tape and reel SN74ALVCH373PWR VB373

-40 ° C to 85 ° C

TVSOP - DGV Tape and reel SN74ALVCH373DGVR VB373

VFBGA - GQN SN74ALVCH373GQNR

Tape and reel VB373

VFBGA - ZQN (Pb-free) SN74ALVCH373ZQNR

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (16 pages)

PAGE 1
SN74ALVCH373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES116H – JULY 1997 – REVISED OCTOBER 2004 FEATURES • • • • • • DGV, DW, OR PW PACKAGE (TOP VIEW) Operates From 1.65 V to 3.6 V Max tpd of 3.3 ns at 3.3 V ±24-mA Output Drive at 3.
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SN74ALVCH373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.
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SN74ALVCH373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES116H – JULY 1997 – REVISED OCTOBER 2004 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range -0.5 4.6 V VI Input voltage range (2) -0.5 4.6 V VO Output voltage range (2) (3) -0.5 VCC + 0.
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SN74ALVCH373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES116H – JULY 1997 – REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -100 µA 1.65 V to 3.6 V 1.65 V IOH = -6 mA 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = -24 mA 3V 2 IOL = 100 µA IOH = -12 mA II(hold) 0.2 1.65 V 0.45 IOL = 6 mA 2.3 V 0.4 2.3 V 0.7 1.65 V 25 1.65 V -25 VI = 0.7 V 2.
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SN74ALVCH373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES116H – JULY 1997 – REVISED OCTOBER 2004 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) FROM (INPUT) PARAMETER TO (OUTPUT) D tpd LE Q VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V MIN MAX MIN 1.7 6.3 1 2 6.1 1 VCC = 3.3 V ± 0.3 V VCC = 2.7 V MAX MIN MAX MIN MAX 4 4 1 3.6 3.8 3.7 1 3.3 UNIT ns ten OE Q 3.4 8.3 1.9 5.
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SN74ALVCH373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCES116H – JULY 1997 – REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open GND CL (see Note A) RL TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUT VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ALVCH373DGVR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74ALVCH373DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74ALVCH373PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALVCH373DGVR TVSOP DGV 20 2000 367.0 367.0 35.0 SN74ALVCH373DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74ALVCH373PWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74ALVCH373ZQNR BGA MICROSTAR JUNIOR ZQN 20 1000 338.1 338.1 20.
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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.