Datasheet

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13
8
(1A−8A)
13
5
(9A−12A, APAR)
Flip-Flop
13
Flip-Flop
5
13
D Q
Parity
Check
12
11
D Q
D Q
XOR
D Q
APAR
APAR
10
(1A−10A)
(1A−11A/YERREN, APAR)
12
(1A−12A)
11A/YERREN
12
1
33
56
29
28
36
30
OE
MODE
CLK
CLKEN
1A−12A,
APAR
PAROE
PARI/O
YERR
1Y2−12Y2
1Y1−12Y1
SN74ALVCH16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
SCES095D – MARCH 1997 – REVISED SEPTEMBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
3