Datasheet

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DESCRIPTION (CONTINUED)
SN74ALVCH16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
SCES095D – MARCH 1997 – REVISED SEPTEMBER 2004
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16903 is characterized for operation from 0 ° C to 70 ° C.
FUNCTION TABLES
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FUNCTION
INPUTS OUTPUTS
OE MODE CLKEN CLK A 1Yn
(1)
–8Yn
(1)
9Yn
(1)
–12Yn
(1)
L L L ↑ H H H
L L L ↑ L L L
L L H ↑ H Y
0
H
L L H ↑ L Y
0
L
L H X X H H H
L H X X L L L
H X X X X Z Z
(1) n = 1 or 2
PARITY FUNCTION
INPUTS
OUTPUT
Σ OF INPUTS
YERR
OE PAROE
(1)
11A/ YERREN
(2)
PARI/O APAR
1A–10A = H
L H L L 0, 2, 4, 6, 8, 10 L H
L H L L 1, 3, 5, 7, 9 L L
L H L L 0, 2, 4, 6, 8, 10 H L
L H L L 1, 3, 5, 7, 9 H H
L H L H 0, 2, 4, 6, 8, 10 L L
L H L H 1, 3, 5, 7, 9 L H
L H L H 0, 2, 4, 6, 8, 10 H H
L H L H 1, 3, 5, 7, 9 H L
H X X X X X H
L X H X X X H
(1) When used as a single device, PAROE must be tied high.
(2) Valid after appropriate number of clock pulses have set internal register
PARI/O FUNCTION
(1)
INPUTS
OUTPUT
Σ OF INPUTS
PARI/O
PAROE APAR
1A–10A = H
L 0, 2, 4, 6, 8, 10 L L
L 1, 3, 5, 7, 9 L H
L 0, 2, 4, 6, 8, 10 H H
L 1, 3, 5, 7, 9 H L
H X X Z
(1) This table applies to the first device of a cascaded pair of
SN74ALVCH16903 devices.
2