Datasheet

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PARAMETER MEASUREMENT INFORMATION
V
OH
V
OL
t
h
t
su
From Output
Under Test
C
L
= 50 pF
(see Note A)
LOAD CIRCUIT
S1
6 V
Open
GND
500 Ω
500 Ω
t
PLH
t
PHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Nte B)
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V1.5 V
1.5 V 1.5 V
2.7 V
0 V
1.5 V 1.5 V
V
OH
V
OL
0 V
1.5 V
V
OL
+ 0.3 V
1.5 V
V
OH
− 0.3 V
0 V
1.5 V
2.7 V
0 V
1.5 V 1.5 V
0 V
2.7 V
0 V
1.5 V 1.5 V
t
w
Input
2.7 V
2.7 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
t
pd
t
PLZ
/t
PZL
t
PHZ
/t
PZH
Open
6 V
GND
TEST S1
t
PHL
(see Note H)
t
PLH
(see Note I)
6 V
6 V
YERR S1
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z
O
= 50 Ω, t
r
≤ 2.5 ns, t
f
≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as t
en
.
G. t
PLH
and t
PHL
are the same as t
pd
.
H. t
PHL
is measured at 1.5 V.
I. t
PLH
is measured at V
OL
+ 0.3 V.
SN74ALVCH16903
3.3-V 12-BIT UNIVERSAL BUS DRIVER
WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
SCES095D – MARCH 1997 – REVISED SEPTEMBER 2004
V
CC
= 2.7 V AND 3.3 V ± 0.3 V
Figure 4. Load Circuit and Voltage Waveforms
10