Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICs74ALVCH SSOP 56

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FEATURES

DESCRIPTION/ORDERING INFORMATION

DGG OR DL PACKAGE

(TOP VIEW)

GND

OEAB

GND

A10

A11

A12

GND

A13

A14

A15

A16

A17

GND

A18

OEBA

CLKENBA

GND

SEL

GND

B10

B11

B12

GND

B13

B14

B15

B16

B17

GND

B18

CLK

GND

SN74ALVCH16524

18-BIT REGISTERED BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES080E – JULY 1996 – REVISED OCTOBER 2004

• Member of the Texas Instruments Widebus™

Family

• UBT™ Transceiver Combines D-Type Latches

and D-Type Flip-Flops for Operation in

Transparent, Latched, Clocked, or

Clock-Enable Mode

• Operates From 1.65 V to 3.6 V

• Max t

of 3.2 ns at 3.3 V

• ±24-mA Output Drive at 3.3 V

• Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• ESD Performance Tested Per JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

This 18-bit universal bus transceiver is designed for

1.65-V to 3.6-V V

operation.

Data flow in each direction is controlled by

output-enable ( OEAB and OEBA) and clock-enable

( CLKENBA) inputs. For the A-to-B data flow, the data

flows through a single buffer. The B-to-A data can

flow through a four-stage pipeline register path, or

through a single register path, depending on the state

of the select ( SEL) input.

Data is stored in the internal registers on the

low-to-high transition of the clock (CLK) input,

provided that the appropriate CLKENBA input is low.

The B-to-A data transfer is synchronized with CLK.

To ensure the high-impedance state during power up or power down, OE should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

Tube SN74ALVCH16524DL

SSOP - DL ALVCH16524

-40 to 85 ° C Tape and reel SN74ALVCH16524DLR

TSSOP - DGG Tape and reel SN74ALVCH16524DGGR ALVCH16524

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus, UBT are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (12 pages)

PAGE 1
SN74ALVCH16524 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES080E – JULY 1996 – REVISED OCTOBER 2004 FEATURES • • • • • • • • DGG OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus™ Family UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enable Mode Operates From 1.65 V to 3.6 V Max tpd of 3.2 ns at 3.3 V ±24-mA Output Drive at 3.
PAGE 2
SN74ALVCH16524 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES080E – JULY 1996 – REVISED OCTOBER 2004 FUNCTION TABLE B-TO-A STORAGE (OEBA = L) INPUTS (1) (2) CLKENBA CLK SEL B OUTPUT A H X X X A0 (1) L ↑ H L L L ↑ H H H L ↑ L L L (2) L ↑ L H H (2) Output level before the indicated steady-state input conditions were established Four positive CLK edges are needed to propagate data from B to A when SEL is low.
PAGE 3
SN74ALVCH16524 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES080E – JULY 1996 – REVISED OCTOBER 2004 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range Except I/O ports (2) MIN MAX -0.5 4.6 -0.5 4.6 -0.5 VCC + 0.5 -0.5 VCC + 0.
PAGE 4
SN74ALVCH16524 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES080E – JULY 1996 – REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -100 µA 1.65 V to 3.6 V 1.65 V IOH = -6 mA 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = -24 mA 3V 2 IOL = 100 µA IOH = -12 mA II(hold) V 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 6 mA 2.3 V 0.4 2.3 V 0.7 IOL = 24 mA II 1.
PAGE 5
SN74ALVCH16524 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES080E – JULY 1996 – REVISED OCTOBER 2004 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V MIN (1) fmax MIN MAX 120 VCC = 2.7 V VCC = 3.3 V ± 0.3 V MIN MAX MIN MAX 125 150 UNIT MHz A B (1) 1 3.9 3.8 1 3.2 CLK A (1) 1 6.1 6.2 1 5.2 ten OEAB or OEBA A or B (1) 1 6.1 6.
PAGE 6
SN74ALVCH16524 18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES080E – JULY 1996 – REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open GND CL (see Note A) RL TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUT VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74ALVCH16524DGGR TSSOP DGG 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.6 1.8 12.0 24.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALVCH16524DGGR TSSOP DGG 56 2000 346.0 346.0 41.
PAGE 10
MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.
PAGE 11
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 12
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