Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICs74ALVCH SSOP 56

www.ti.com

FEATURES

DESCRIPTION/ORDERING INFORMATION

DGG OR DL PACKAGE

(TOP VIEW)

OEAB

LEAB

GND

A10

A11

A12

GND

A13

A14

A15

A16

A17

GND

A18

OEBA

LEBA

GND

CLKAB

GND

B10

B11

B12

GND

B13

B14

B15

B16

B17

GND

B18

CLKBA

GND

Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are

SN74ALVCH16501

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES024J – JULY 1995 – REVISED OCTOBER 2004

• Member of the Texas Instruments Widebus™

Family

• UBT™ Transceiver Combines D-Type Latches

and D-Type Flip-Flops for Operation in

Transparent, Latched, or Clocked Modes

• Operates From 1.65 V to 3.6 V

• Max t

of 3.9 ns at 3.3 V

• ± 24-mA Output Drive at 3.3 V

• Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• ESD Protection Exceeds JESD 22

- 2000-V Human-Body Model (A114-A)

- 200-V Machine Model (A115-A)

This 18-bit universal bus transceiver is designed for

1.65-V to 3.6-V V

operation.

Data flow in each direction is controlled by

output-enable (OEAB and OEBA), latch-enable

(LEAB and LEBA), and clock (CLKAB and CLKBA)

inputs. For A-to-B data flow, the device operates in

the transparent mode when LEAB is high. When

LEAB is low, the A data is latched if CLKAB is held at

a high or low logic level. If LEAB is low, the A data is

stored in the latch/flip-flop on the low-to-high

transition of CLKAB. When OEAB is high, the outputs

are active. When OEAB is low, the outputs are in the

high-impedance state.

complementary (OEAB is active high, and OEBA is active low).

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

Tube SN74ALVCH16501DL

SSOP - DL ALVCH16501

Tape and reel SN74ALVCH16501DLR

-40 ° C to 85 ° C TSSOP - DGG Tape and reel SN74ALVCH16501DGGR ALVCH16501

VFBGA - GQL SN74ALVCH16501KR

Tape and reel VH501

VFBGA - ZQL (Pb-free) 74ALVCH16501ZQLR

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus, UBT are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (16 pages)

PAGE 1
SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES024J – JULY 1995 – REVISED OCTOBER 2004 FEATURES • • • • • • • • DGG OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus™ Family UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes Operates From 1.65 V to 3.6 V Max tpd of 3.9 ns at 3.3 V ±24-mA Output Drive at 3.
PAGE 2
SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES024J – JULY 1995 – REVISED OCTOBER 2004 DESCRIPTION/ORDERING INFORMATION (CONTINUED) To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pullup resistor, and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
PAGE 3
SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES024J – JULY 1995 – REVISED OCTOBER 2004 FUNCTION TABLE (1) INPUTS (1) (2) (3) OEAB LEAB CLKAB A OUTPUT B L X X X Z H H X L L H H X H H H L ↑ L L H L ↑ H H H L H X B0 (2) H L L X B0 (3) A-to-B data flow is shown; B-to-A flow is similar, but uses OEBA, LEBA, and CLKBA.
PAGE 4
SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES024J – JULY 1995 – REVISED OCTOBER 2004 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range MIN MAX -0.5 4.6 Except I/O ports (2) -0.5 4.6 I/O ports (2) (3) -0.5 VCC + 0.5 -0.5 VCC + 0.
PAGE 5
SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES024J – JULY 1995 – REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -100 µA 1.65 V to 3.6 V 1.65 V IOH = -6 mA 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = -24 mA 3V 2 IOL = 100 µA IOH = -12 mA II(hold) V 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 6 mA 2.3 V 0.4 2.3 V 0.7 IOL = 24 mA II 1.
PAGE 6
SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES024J – JULY 1995 – REVISED OCTOBER 2004 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) A or B B or A fmax tpd VCC = 2.5 V ± 0.2 V MIN MAX 150 LE A or B CLK VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN MAX 150 MIN UNIT MAX 150 MHz 1 4.8 4.5 1 3.9 1.1 5.7 5.3 1.3 4.6 1.2 6.1 5.6 1.4 4.
PAGE 7
SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES024J – JULY 1995 – REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open GND CL (see Note A) RL TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUT VCC 1.8 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 10-Oct-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device 74ALVCH16501ZQLR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant BGA MI CROSTA R JUNI OR ZQL 56 1000 330.0 16.4 4.8 7.3 1.5 8.0 16.0 Q1 SN74ALVCH16501DGGR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 10-Oct-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74ALVCH16501ZQLR BGA MICROSTAR JUNIOR ZQL 56 1000 333.2 345.9 28.6 SN74ALVCH16501DGGR TSSOP DGG 56 2000 367.0 367.0 45.
PAGE 12
PAGE 13
PAGE 14
PAGE 15
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 16
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.