Datasheet

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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
GQL PACKAGE
(TOP VIEW)
A
B
C
D
E
F
G
H
J
K
1 2 3 4 5 6
1OE
1LE
1D1
To Seven Other Channels
1Q1
2OE
2LE
2D1
2Q1
To Seven Other Channels
1
48
47
24
25
36
C1
1D
132
C1
1D
Pin numbers shown are for the DGG and DL packages.
SN74ALVCH162373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES583A – JULY 2004 – REVISED OCTOBER 2004
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
XXX
XXX
TERMINAL ASSIGNMENTS
(1)
1 2 3 4 5 6
A 1 OE NC NC NC NC 1LE
B 1Q2 1Q1 GND GND 1D1 1D2
C 1Q4 1Q3 V
CC
V
CC
1D3 1D4
D 1Q6 1Q5 GND GND 1D5 1D6
E 1Q8 1Q7 1D7 1D8
F 2Q1 2Q2 2D2 2D1
G 2Q3 2Q4 GND GND 2D4 2D3
H 2Q5 2Q6 V
CC
V
CC
2D6 2D5
J 2Q7 2Q8 GND GND 2D8 2D7
K 2 OE NC NC NC NC 2LE
(1) NC - No internal connection
FUNCTION TABLE
(each 8-bit section)
INPUTS
OUTPUT
Q
OE LE D
L H H H
L H L L
L L X Q
0
H X X Z
LOGIC DIAGRAM (POSITIVE LOGIC)
2