Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICs74ALVCH SSOP 48

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FEATURES

DESCRIPTION

DGG, DGV, OR DL PACKAGE

(TOP VIEW)

GND

Y10

GND

Y11

Y12

Y13

Y14

GND

Y15

Y16

CLK

GND

A10

GND

A11

A12

A13

A14

GND

A15

A16

NC − No internal connection

Data flow from A to Y is controlled by the output-enable ( OE) input. The device operates in the transparent mode

SN74ALVCH162334

16-BIT UNIVERSAL BUS DRIVER

WITH 3-STATE OUTPUTS

SCES120H – JULY 1997 – REVISED SEPTEMBER 2004

• Member of the Texas Instruments Widebus™

Family

• EPIC™ (Enhanced-Performance Implanted

CMOS) Submicron Process

• Output Port Has Equivalent 26- Ω Series

Resistors, So No External Resistors Are

Required

• Designed to Comply With JEDEC 168-Pin and

200-Pin SDRAM Buffered DIMM Specification

• ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

• Package Options Include Plastic Shrink

Small-Outline (DL), Thin Shrink Small-Outline

(DGG), and Thin Very Small-Outline (DGV)

Packages

NOTE: For tape-and-reel order entry, the DGGR package is

abbreviated to GR, and the DGVR package is abbreviated

to VR.

This 16-bit universal bus driver is designed for 1.65-V

to 3.6-V V

operation.

when the latch-enable ( LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at

a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of

CLK. When OE is high, the outputs are in the high-impedance state.

The output port includes equivalent 26- Ω series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH162334 is characterized for operation from -40 ° C to 85 ° C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus, EPIC are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (15 pages)

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www.ti.
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SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.
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SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES120H – JULY 1997 – REVISED SEPTEMBER 2004 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range -0.5 4.6 V VI Input voltage range (2) -0.5 4.6 V VO Output voltage range (2) (3) -0.5 VCC + 0.
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SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES120H – JULY 1997 – REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -100 µA VOH 1.65 V to 3.6 V II(hold) VCC - 0.2 1.65 V 1.2 IOH = -4 mA 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = -8 mA 2.7 V 2 IOH = -12 mA 3V 2 IOL = 100 µA V 1.65 V to 3.6 V 0.2 IOL = 2 mA 1.65 V 0.45 IOL = 4 mA 2.3 V 0.4 2.
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SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES120H – JULY 1997 – REVISED SEPTEMBER 2004 TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3) VCC = 1.8 V MIN MAX fclock tw tsu th (1) Setup time Hold time MIN MAX (1) Clock frequency Pulse duration VCC = 2.5 V ± 0.2 V VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN 150 150 MHz LE low (1) 3.3 3.3 3.3 CLK high or low (1) 3.
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SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES120H – JULY 1997 – REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC = 1.
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SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES120H – JULY 1997 – REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
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SN74ALVCH162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS www.ti.com SCES120H – JULY 1997 – REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input Input 1.5 V 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74ALVCH162334GR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 SN74ALVCH162334VR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALVCH162334GR TSSOP DGG 48 2000 346.0 346.0 41.0 SN74ALVCH162334VR TVSOP DGV 48 2000 346.0 346.0 33.
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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.
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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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