Datasheet

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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
GQL OR ZQL PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
21 3 4 65
K
SN74ALVCH162268
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as
possible, and OE should be tied to V
CC
through a pullup resistor; the minimum value of the resistor is determined
by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the
outputs cannot be determined prior to the arrival of the first clock pulse.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
TERMINAL ASSIGNMENTS
1 2 3 4 5 6
A 2B3 CLKEN1B OEA OEB CLKENA2 2B4
B 2B1 2B2 GND GND 2B5 2B6
C A2 A1 V
CC
V
CC
2B7 2B8
D A4 A3 GND GND 2B9 2B10
E A6 A5 2B11 2B12
F A7 A8 1B11 1B12
G A9 A10 GND GND 1B9 1B10
H A11 A12 V
CC
V
CC
1B7 1B8
J 1B1 1B2 GND GND 1B5 1B6
K 1B3 CLKEN2B SEL CLK CLKENA1 1B4
2