Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICs74ALVCH SSOP 56

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FEATURES

DESCRIPTION/ORDERING INFORMATION

DGG OR DL PACKAGE

(TOP VIEW)

OEA

CLKEN1B

2B3

GND

2B2

2B1

GND

A10

A11

A12

1B1

1B2

GND

1B3

CLKEN2B

SEL

OEB

CLKENA2

2B4

GND

2B5

2B6

2B7

2B8

2B9

GND

2B10

2B11

2B12

1B12

1B11

1B10

GND

1B9

1B8

1B7

1B6

1B5

GND

1B4

CLKENA1

CLK

SN74ALVCH162268

12-BIT TO 24-BIT REGISTERED BUS EXCHANGER

WITH 3-STATE OUTPUTS

SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004

• Member of the Texas Instruments Widebus™

Family

• Operates From 1.65 V to 3.6 V

• Max t

of 4.8 ns at 3.3 V

• ± 24-mA Output Drive at 3.3 V

• B-Port Outputs Have Equivalent 26- Ω Series

Resistors, So No External Resistors Are

Required

• Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

This 12-bit to 24-bit registered bus exchanger is

designed for 1.65-V to 3.6-V V

operation.

The SN74ALVCH162268 is used for applications in

which data must be transferred from a narrow

high-speed bus to a wide, lower-frequency bus.

The device provides synchronous data exchange

between the two ports. Data is stored in the internal

registers on the low-to-high transition of the clock

(CLK) input when the appropriate clock-enable

( CLKEN) inputs are low. The select ( SEL) line is

synchronous with CLK and selects 1B or 2B input

data for the A outputs.

For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single

storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be

presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables

( OEA, OEB). These control terminals are registered, so bus direction changes are synchronous with CLK.

The B outputs, which are designed to sink up to 12 mA, include equivalent 26- Ω resistors to reduce overshoot

and undershoot.

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

Tube SN74ALVCH162268DL

SSOP - DL ALVCH162268

Tape and reel SN74ALVCH162268DLR

-40 ° C to 85 ° C TSSOP - DGG Tape and reel SN74ALVCH162268GR ALVCH162268

VFBGA - GQL SN74ALVCH162268KR

Tape and reel VH2268

VFBGA - ZQL (Pb-free) 74ALVCH162268ZQLR

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (16 pages)

PAGE 1
SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004 FEATURES • • • • • • • • Member of the Texas Instruments Widebus™ Family Operates From 1.65 V to 3.6 V Max tpd of 4.8 ns at 3.3 V ±24-mA Output Drive at 3.
PAGE 2
SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004 DESCRIPTION/ORDERING INFORMATION (CONTINUED) To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible, and OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.
PAGE 4
SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004 LOGIC DIAGRAM (POSITIVE LOGIC) 29 CLK 2 CLKEN1B 27 CLKEN2B CLKENA1 30 55 C1 CLKENA2 56 1D OEB C1 SEL 28 1D 1 OEA CE 1D C1 1D C1 G1 A1 1 CE C1 1D 1D CE C1 1D C1 1D CE C1 1D 1 of 12 Channels Pin numbers shown are for the DGG and DL packages.
PAGE 5
www.ti.com SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range MIN MAX -0.5 4.6 Except I/O ports (2) -0.5 4.6 I/O ports (2) (3) -0.5 VCC + 0.5 -0.5 VCC + 0.
PAGE 6
SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004 RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage VCC = 1.65 V to 1.95 V VIH High-level input voltage MIN MAX 1.65 3.6 Low-level input voltage VI Input voltage VO Output voltage High-level output current (A port) IOH High-level output current (B port) VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 IOL Low-level output current (B port) VCC = 2.
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SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -100 µA IOH = -6 mA 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = -24 mA 3V 2 IOH = -100 µA 1.65 V to 3.6 V A port B port 1.65 V 1.2 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = -8 mA 2.
PAGE 8
SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004 TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V ± 0.2 V MIN fclock Clock frequency tw Pulse duration, CLK high or low tsu Setup time th Hold time VCC = 2.7 V MAX MIN 120 3.3 MAX VCC = 3.3 V ± 0.3 V MIN 125 150 3.3 3.3 3.4 A data before CLK↑ 4.5 4 B data before CLK↑ 0.
PAGE 9
SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS www.ti.com SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open GND CL (see Note A) RL TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUT VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ALVCH162268GR Package Package Pins Type Drawing TSSOP DGG 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.6 1.8 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALVCH162268GR TSSOP DGG 56 2000 367.0 367.0 45.
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PAGE 15
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 16
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.