Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch D type, Addressable Three-state SSOP 56

www.ti.com

FEATURES

DESCRIPTION

DGG OR DL PACKAGE

(TOP VIEW)

OEA

LE1B

2B3

GND

2B2

2B1

GND

A10

A11

A12

1B1

1B2

GND

1B3

LE2B

SEL

OE2B

LEA2B

2B4

GND

2B5

2B6

2B7

2B8

2B9

GND

2B10

2B11

2B12

1B12

1B11

1B10

GND

1B9

1B8

1B7

1B6

1B5

GND

1B4

LEA1B

OE1B

Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The

SN74ALVCH162260

12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH

WITH 3-STATE OUTPUTS

SCAS570I – MARCH 1996 – REVISED AUGUST 2004

• Member of the Texas Instruments Widebus™

Family

• EPIC™ (Enhanced-Performance Implanted

CMOS) Submicron Process

• B-Port Outputs Have Equivalent 26-Ω Series

Resistors, So No External Resistors Are

Required

• ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

• Package Options Include Thin-Shrink

Small-Outline (DGG) and Plastic Shrink

Small-Outline (DL) Packages

NOTE:

For tape-and-reel order entry: The DGGR package is

abbreviated to GR.

This 12-bit to 24-bit multiplexed D-type latch is

designed for 1.65-V to 3.6-V V

operation.

The SN74ALVCH162260 is used in applications in

which two separate data paths must be multiplexed

onto, or demultiplexed from, a single data path.

Typical applications include multiplexing and/or

demultiplexing address and data information in

microprocessor or bus-interface applications. This

device also is useful in memory-interleaving

applications.

output-enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2B

control signals also allow bank control in the A-to-B direction.

Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B,

LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the latch is

transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched

until the latch-enable input is returned high.

The B outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot

and undershoot.

To ensure the high-impedance state during power up or power down, OE should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH162260 is characterized for operation from -40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus, EPIC are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (16 pages)

PAGE 1
www.ti.
PAGE 2
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.
PAGE 3
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.
PAGE 4
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS570I – MARCH 1996 – REVISED AUGUST 2004 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range MIN MAX -0.5 4.6 Except I/O ports (2) -0.5 4.6 I/O ports (2) (3) -0.5 VCC + 0.5 -0.5 VCC + 0.
PAGE 5
www.ti.com SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS570I – MARCH 1996 – REVISED AUGUST 2004 RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage VCC = 1.65 V to 1.95 V VIH High-level input voltage MIN MAX 1.65 3.6 UNIT V 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 V 0.35 × VCC VCC = 1.65 V to 1.95 V VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 VI Input voltage 0 VCC V VO Output voltage 0 VCC v VCC = 2.
PAGE 6
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS570I – MARCH 1996 – REVISED AUGUST 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -100 µA 1.65 V to 3.6 V IOH = -6 mA 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = -24 mA 3V 2 IOH = -100 µA 1.65 V to 3.6 V A port VOL B port II 1.65 V 1.2 2.3 V 1.9 2.3 V 1.7 3V 2.4 IOH = -8 mA 2.
PAGE 7
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS570I – MARCH 1996 – REVISED AUGUST 2004 TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3) VCC = 2.5 V ± 0.2 V VCC = 1.8 V MIN MAX MIN (1) VCC = 2.7 V MAX MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX fclock Clock frequency tw Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high 150 150 MHz (1) 3.3 3.3 3.
PAGE 8
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS570I – MARCH 1996 – REVISED AUGUST 2004 PARAMETER MEASUREMENT INFORMATION VCC = 1.
PAGE 9
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS570I – MARCH 1996 – REVISED AUGUST 2004 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.
PAGE 10
SN74ALVCH162260 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS www.ti.com SCAS570I – MARCH 1996 – REVISED AUGUST 2004 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V From Output Under Test 6V Open S1 500 Ω GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74ALVCH162260DLR SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 SN74ALVCH162260GR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALVCH162260DLR SSOP DL 56 1000 346.0 346.0 49.0 SN74ALVCH162260GR TSSOP DGG 56 2000 346.0 346.0 41.
PAGE 14
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 15
MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.
PAGE 16
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.