Datasheet

SN74ALVC7804
512 × 18
FIRST-IN, FIRST-OUT MEMORY
SCAS432 – JANUARY 1995
10
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Input
V
OH
V
OL
t
h
t
su
From Output
Under Test
C
L
= 50 pF
(see Note A)
LOAD CIRCUIT FOR OUTPUTS
S1
6 V
Open
GND
500
500
t
PLH
t
PHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V1.5 V
1.5 V 1.5 V
3 V
0 V
1.5 V 1.5 V
V
OH
V
OL
0 V
1.5 V
V
OL
+ 0.3 V
1.5 V
V
OH
– 0.3 V
0 V
1.5 V
3 V
0 V
1.5 V 1.5 V
0 V
3 V
0 V
1.5 V 1.5 V
t
w
3 V
3 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z
O
= 50 , t
r
2.5 ns, t
f
2.5 ns.
3-STATE OUTPUTS (ANY Q)
PARAMETER
R1, R2 C
L
S1
t
t
PZH
500
50
p
F
GND
t
en
t
PZL
500
50
pF
6 V
t
di
t
PHZ
500
50
p
F
GND
t
dis
t
PLZ
500
50
pF
6 V
t
pd
t
PLH
/t
PHL
500 50 pF Open
Includes probe and test-fixture capacitance
Figure 5. Standard CMOS Outputs (FULL, EMPTY, HF, AF/AE)