Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate AND gate 74ALVC SOIC 14

www.ti.com

FEATURES

DESCRIPTION/ORDERING INFORMATION

or Y =

A + B

in positive logic.

D, DGV, NS, OR PW PACKAGE

(TOP VIEW)

GND

RGY PACKAGE

(TOP VIEW)

1 14

7 8

GND

SN74ALVC08

QUADRUPLE 2-INPUT POSITIVE-AND GATE

SCES101I – JULY 1997 – REVISED OCTOBER 2004

• Operates From 1.65 V to 3.6 V

• Max t

of 2.9 ns at 3.3 V

• ± 24-mA Output Drive at 3.3 V

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

This quadruple 2-input positive-AND gate is designed

for 1.65-V to 3.6-V V

operation.

The device performs the Boolean function Y = A · B

ORDERING INFORMATION

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

QFN - RGY Tape and reel SN74ALVC08RGYR VA08

Tube SN74ALVC08D

SOIC - D ALVC08

Tape and reel SN74ALVC08DR

-40 ° C to 85 ° C

SOP - NS Tape and reel SN74ALVC08NSR ALVC08

TSSOP - PW Tape and reel SN74ALVC08PWR VA08

TVSOP - DGV Tape and reel SN74ALVC08DGVR VA08

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A B

H H H

L X L

X L L

LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (18 pages)

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SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCES101I – JULY 1997 – REVISED OCTOBER 2004 FEATURES 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y This quadruple 2-input positive-AND gate is designed for 1.65-V to 3.6-V VCC operation. 1B 1Y 2A 2B 2Y 1 14 2 13 4B 3 12 4A 4 11 4Y 5 6 10 3B 9 3A 7 8 3Y The device performs the Boolean function Y = A · B or Y = A + B in positive logic.
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SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCES101I – JULY 1997 – REVISED OCTOBER 2004 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range -0.5 4.6 V VI Input voltage range (2) -0.5 4.6 V VO Output voltage range (2) (3) -0.5 VCC + 0.
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SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCES101I – JULY 1997 – REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = -100 µA 1.65 V to 3.6 V 1.65 V IOH = -6 mA 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = -24 mA 3V 2 IOL = 100 µA IOH = -12 mA VOL 0.2 1.65 V 0.45 IOL = 6 mA 2.3 V 0.4 2.3 V 0.
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SN74ALVC08 QUADRUPLE 2-INPUT POSITIVE-AND GATE www.ti.com SCES101I – JULY 1997 – REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open GND CL (see Note A) RL TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUT VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2009 retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74ALVC08DGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74ALVC08DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74ALVC08DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALVC08DGVR TVSOP DGV 14 2000 367.0 367.0 35.0 SN74ALVC08DR SOIC D 14 2500 333.2 345.9 28.6 SN74ALVC08DR SOIC D 14 2500 367.0 367.0 38.0 SN74ALVC08NSR SO NS 14 2000 367.0 367.0 38.0 SN74ALVC08PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74ALVC08RGYR VQFN RGY 14 3000 367.0 367.0 35.
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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.