Datasheet

SN54AS867, SN54AS869
SN74ALS867A, SN74ALS869, SN74AS867, SN74AS869
SYNCHRONOUS 8-BIT UP/DOWN COUNTERS
SDAS115C – DECEMBER 1982 – REVISED JANUARY 1995
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical clear, preset, count, and inhibit sequences
The following sequence is illustrated below:
1. Clear outputs to zero (SN74ALS867A and ′AS867 are asynchronous;
SN74ALS869 and ′AS869 are synchronous.)
2. Preset to binary 252
3. Count up to 253, 254, 255, 0, 1, and 2
4. Count down to 1, 0, 255, 254, 253, and 252
5. Inhibit
C
Async
Clear
D
E
F
CLK
ENP
ENT
Q
A
Q
B
Q
C
Q
D
RCO
Data
Inputs
Outputs
Q
E
Q
F
Q
G
Q
H
Count Down
G
H
B
A
S1
S0
Preset
Sync
Clear
252 253 255254 255 254 253 25201210
Count Up Inhibit
†
†
ENT
and ENP both must be low for counting to occur.