Datasheet
SN54ALS299, SN74ALS299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
SDAS220B – DECEMBER 1982 – REVISED DECEMBER 1994
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN54ALS299 SN74ALS299
UNIT
MIN MAX MIN MAX
UNIT
f
clock
Clock frequency (at 50% duty cycle) 0 17 0 30 MHz
t
Pulse duration
CLK high or low 22 16.5
ns
t
w
P
u
lse
d
u
ration
CLR low 12 10
ns
↑
S0 or S1 25 20
t
Setup time before CLK
↑
Serial or parallel data
High 18 16
ns
t
su
S
er
i
a
l
or para
ll
e
l
d
a
t
a
Low 15 6
ns
Inactive-state setup time before CLK↑
†
CLR 15 15
t
h
Hold time after CLK↑
S0 or S1 0 0
ns
t
h
H
o
ld
ti
me a
ft
er
CLK↑
Serial or parallel data
0 0
ns
†
Inactive-state setup time is also referred to as recovery time.
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
V
CC
= 4.5 V to 5.5 V,
C
L
= 50 pF,
R1 = 500 Ω
,
R2 = 500 Ω,
T
A
= MIN to MAX
‡
UNIT
SN54ALS299 SN74ALS299
MIN MAX MIN MAX
f
max
17 30 MHz
t
PLH
CLK
QQ
2 19 4 13
ns
t
PHL
CLK
Q
A
–
Q
H
4 25 7 19
ns
t
PLH
CLK
Q
′
or Q
′
2 21 5 15
ns
t
PHL
CLK
Q
A′
or
Q
H′
4 25 8 18
ns
t
PHL
CLR
Q
A
–Q
H
6 29 6 22
ns
t
PHL
CLR
Q
A′
or Q
H′
6 29 6 22
ns
t
PZH
OE1 OE2
QQ
5 22 6 16
ns
t
PZL
OE1
,
OE2
Q
A
–
Q
H
6 27 8 22
ns
t
PZH
S0 S1
QQ
5 27 7 17
ns
t
PZL
S0
,
S1
Q
A
–
Q
H
6 26 8 22
ns
t
PHZ
OE1 OE2
QQ
1 15 1 8
ns
t
PLZ
OE1
,
OE2
Q
A
–
Q
H
4 38 5 15
ns
t
PHZ
S0 S1
Q
A
Q
H
1 16 1 12
ns
t
PLZ
S0
,
S1
Q
A
–
Q
H
4 34 8 25
ns
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.