Datasheet

SN54ALS299, SN74ALS299
8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS
WITH 3-STATE OUTPUTS
SDAS220B – DECEMBER 1982 – REVISED DECEMBER 1994
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
FUNCTION TABLE
MODE
INPUTS I/O PORTS OUTPUTS
MODE
CLR S1 S0 OE1
OE2
CLK SL SR A/Q
A
B/Q
B
C/Q
C
D/Q
D
E/Q
E
F/Q
F
G/Q
G
H/Q
H
Q
A
Q
H
Clear
L
L
L
X
L
H
L
X
H
L
L
X
L
L
X
X
X
X
X
X
X
X
X
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
X
L
L
L
L
L
L
Hold
H
H
L
X
L
X
L
L
L
L
X
L
X
X
X
X
Q
A0
Q
A0
Q
B0
Q
B0
Q
C0
Q
C0
Q
D0
Q
D0
Q
E0
Q
E0
Q
F0
Q
F0
Q
G0
Q
G0
Q
H0
Q
H0
Q
A0
Q
A0
Q
H0
Q
H0
Shift
Right
H
H
L
L
H
H
L
L
L
L
X
X
H
L
H
L
Q
An
Q
An
Q
Bn
Q
Bn
Q
Cn
Q
Cn
Q
Dn
Q
Dn
Q
En
Q
En
Q
Fn
Q
Fn
Q
Gn
Q
Gn
H
L
Q
Gn
Q
Gn
Shift
Left
H
H
H
H
L
L
L
L
L
L
H
L
X
X
Q
Bn
Q
Bn
Q
Cn
Q
Cn
Q
Dn
Q
Dn
Q
En
Q
En
Q
Fn
Q
Fn
Q
Gn
Q
Gn
Q
Hn
Q
Hn
H
L
Q
Bn
Q
Bn
H
L
Load H H H X X X X a b c d e f g h a h
NOTE: a ...h = the level of the steady-state input at inputs A through H, respectively. This data is loaded into the flip-flops while the flip-flop outputs
are isolated from the I/O terminals.
When one or both output-enable inputs are high, the eight I/O terminals are disabled to the high-impedance state; however, sequential operation
or clearing of the register is not affected.
logic symbol
SRG8
M
0
3
R
9
6
14
5
15
4
8
2
3
0
1
S0
1
19
S1
12
CLK
5, 13
1,4D
11
SR
3,4D
7
6, 13
3,4D
13
17
12, 13
2,4D
18
SL
3,4D
16
&
3
EN13
C4/1/2
Q
A
Q
H
CLR
OE1
OE2
A/Q
A
H/Q
H
B/Q
B
C/Q
C
D/Q
D
E/Q
E
F/Q
F
G/Q
G
Z5
Z6
Z12
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.