Datasheet




SDAS216A − APRIL 1982 − REVISED DECEMBER 1994
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
logic symbol
†
G
MUX
0
3
0
14
A
1
2
B
EN
1
15
1Y
7
0
6
1C0
1
5
1C1
2
4
1C2
3
3
1C3
10
2C0
11
2C1
12
2C2
13
2C3
2Y
9
1OE
2OE
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram (positive logic)
Data 2
Select
Data 1
2OE
2C3
2C2
2C1
2C0
A
B
1C3
1C2
1C1
1C0
1OE
1Y
1
6
5
4
3
2
14
10
11
12
13
15
7
2Y
9
Pin numbers shown are for the D, J, and N packages.