Datasheet

SN74ALS166
PARALLEL-LOAD 8-BIT SHIFT REGISTER
SDAS156D – APRIL 1982 – REVISED AUGUST 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT FOR OUTPUT UNDER TEST
TEST TABLE FOR SYNCHRONOUS INPUTS
SH/LD
H0 V
4.5 V
Q
H
at t
n + 1
Q
H
at t
n + 1
VOLTAGE WAVEFORMS
R
L
= 500 Ω
C
L
= 50 pF
(see Note A)
From Output
Under Test
Test
Point
3.5 V
0.3 V
3.5 V
0.3 V
3.5
0.3 V
V
OH
V
OL
t
w(clear)
1.3 V 1.3 V
t
n + 1
(see Note D)
t
n
t
n
t
n + 1
t
w(CLK)
t
su
t
h
CLR
(see Note C)
CLK
(see Note E)
Data Input
(see Test Table)
Output Q
H
t
PHL
t
PLH
t
PHL
Serial input
DATA INPUT
FOR TEST
OUTPUT TESTED
(see Note B)
1.3 V 1.3 V 1.3 V
t
su
t
h
1.3 V1.3 V 1.3 V1.3 V
NOTES: A. C
L
includes probe and jig capacitance.
B. Propagation delay times (t
PLH
and t
PHL
) are measured at t
n+1
. Proper shifting of data is verified at t
n+8
with a functional test.
C. A clear pulse is applied prior to each test.
D. t
n
= bit time before clocking transition, t
n+1
= bit time after one clocking transition, and t
n+8
= bit time after eight clocking transitions.
E. The clock pulse has the following characteristics: t
w(clock)
≤ 20 ns and PRR = 1 MHz. The clear pulse has the following
characteristics: t
w(clear)
≤ 20 ns.
F. All pulse generators have the following characteristics: Z
O
≈ 50 Ω; t
r
= t
f
= 2 ns. Duty cycle = 50% when testing f
max
.
1.3 V
Figure 1. Load Circuit and Voltage Waveforms