Datasheet

SN74ALS166
PARALLEL-LOAD 8-BIT SHIFT REGISTER
SDAS156D – APRIL 1982 – REVISED AUGUST 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
CLR
SRG8
R
9
M1 [Shift]
15
M2 [Load]
6
CLK INH
7
CLK
C3/1
2, 3D
3
B
4
C
5
D
10
E
11
F
12
G
14
H
1, 3D
1
SER
2, 3D
2
A
13
≥1
Q
H
SH/LD
†
This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
R
1A
C1
1S
R
1A
C1
1S
R
1A
C1
1S
R
1A
C1
1S
R
1A
C1
1S
R
1A
C1
1S
R
1A
C1
1S
R
1A
C1
1S
15
9
7
6
13
SH/LD
CLR
CLK
CLK INH
Q
H
1234510111214
SER A B C D E F G H