Datasheet

SN54ALS139, SN74ALS139
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS
SDAS204A – APRIL 1982 – REVISED DECEMBER 1994
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbols (alternatives)
†
X/Y
1
2
1A
3
1B
13
2B
EN
1
15
14
2A
1Y0
4
0
1Y1
5
1
1Y2
6
2
1Y3
7
3
2Y0
12
2Y1
11
2Y2
10
2Y3
9
G
3
0
1G
2G
DMUX
0
2
1A
1
3
1B
13
2B
1
15
14
2A
1Y0
4
0
1Y1
5
1
1Y2
6
2
1Y3
7
3
2Y0
12
2Y1
11
2Y2
10
2Y3
9
1G
2G
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram (positive logic)
Select
Inputs
Select
Inputs
2B
2A
Enable 2G
1B
1A
Enable 1G
Data
Outputs
2Y3
2Y2
2Y1
2Y0
1Y3
1Y2
1Y1
1Y0
1
2
3
15
14
13
4
5
6
7
12
11
10
9
Pin numbers shown are for the D, J, and N packages.