Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Preset/reset Differential SOIC 16







SDAS199A − APRIL 1982 − REVISED DECEMBER 1994

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

• Fully Buffered to Offer Maximum Isolation

From External Disturbance

• Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Chip

Carriers (FK), and Standard Plastic (N) and

Ceramic (J) 300-mil DIPs

TYPE

TYPICAL MAXIMUM

CLOCK

FREQUENCY

(MHz)

TYPICAL POWER

DISSIPATION

PER FLIP-FLOP

(mW)

′ALS112A 50 6

description

These devices contain two independent J-K

negative-edge-triggered flip-flops. A low level at

the preset (PRE

) or clear (CLR) inputs sets or

resets the outputs, regardless of the levels of the

other inputs. When PRE

and CLR are inactive

(high), data at the J and K inputs meeting the

setup-time requirements is transferred to the

outputs on the negative-going edge of the clock

pulse (CLK). Clock triggering occurs at a voltage

level and is not directly related to the fall time of the

clock pulse. Following the hold-time interval, data

at the J and K inputs may be changed without

affecting the levels at the outputs. These versatile

flip-flops can perform as toggle flip-flops by tying

J and K high.

The SN54ALS112A is characterized for operation over the full military temperature range of −55°C to 125°C.

The SN74ALS112A is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUTS

PRE CLR CLK J K Q Q

L H X X X H L

H LXXXLH

L LXXXH

†

H H ↓ LLQ

H H ↓ HLHL

H H ↓ LHLH

H H ↓ H H Toggle

H H H X X Q

†

The output levels in this configuration may not meet the

minimum levels for V

. Furthermore, this configuration is

nonstable; that is, it does not persist when either PRE

CLR

returns to its inactive (high) level.

SN54ALS112A ...J PACKAGE

SN74ALS112A ...D OR N PACKAGE

(TOP VIEW)

SN54ALS112A . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

1CLK

1PRE

GND

1CLR

2CLR

2CLK

2PRE

3212019

910111213

2CLR

2CLK

1PRE

1CLK

1CLR

GND

2PRE

  !"#$%! & '("")% $& ! *(+,'$%! -$%).

"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&

&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)

%)&%3 ! $,, *$"$#)%)"&.

Summary of content (17 pages)

PAGE 1
SDAS199A − APRIL 1982 − REVISED DECEMBER 1994 • SN54ALS112A . . . J PACKAGE SN74ALS112A . . .
PAGE 2
SDAS199A − APRIL 1982 − REVISED DECEMBER 1994 logic symbol† 1PRE 1J 1CLK 1K 1CLR 2PRE 2J 2CLK 2K 2CLR 4 3 S 5 1J 1 2 15 1Q C1 6 1K 1Q R 10 9 11 2Q 13 12 7 2Q 14 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages.
PAGE 3
SDAS199A − APRIL 1982 − REVISED DECEMBER 1994 recommended operating conditions SN54ALS112A SN74ALS112A MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.7 0.8 V High-level output current −0.4 −0.
PAGE 4
SDAS199A − APRIL 1982 − REVISED DECEMBER 1994 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.
PAGE 5
SDAS199A − APRIL 1982 − REVISED DECEMBER 1994 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS 3.5 V High-Level Pulse 1.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74ALS112ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74ALS112ANSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ALS112ADR SN74ALS112ANSR SOIC D 16 2500 333.2 345.9 28.6 SO NS 16 2000 367.0 367.0 38.
PAGE 11
PAGE 12
PAGE 13
PAGE 14
PAGE 15
PAGE 16
PAGE 17
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.