Datasheet

 
  
  
SCLS417H − JUNE 1998 − REVISED SEPTEMBER 2003
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
T
A
= 25°C SN54AHCT594 SN74AHCT594
UNIT
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP MAX MIN MAX MIN MAX
UNIT
V
OH
I
OH
= −50 mA
4.5 V
4.4 4.5 4.4 4.4
V
V
OH
I
OH
= −8 mA
4.5 V
3.94 3.8 3.8
V
V
OL
I
OL
= 50 mA
4.5 V
0.1 0.1 0.1
V
V
OL
I
OL
= 8 mA
4.5 V
0.36 0.44 0.44
V
I
I
V
I
= 5.5 V or GND 0 V to 5.5 V ±0.1 ±1* ±1 mA
I
CC
V
I
= V
CC
or GND, I
O
= 0 5.5 V 2 20 20 mA
∆I
CC
†
One input at 3.4 V,
Other inputs at V
CC
or GND
5.5 V 2 2.2 2.2 mA
C
i
V
I
= V
CC
or GND 5 V 2 10 10 pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested at V
CC
= 0 V.
†
This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or V
CC
.
timing requirements over recommended operating free-air temperature range,
V
CC
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
T
A
= 25°C SN54AHCT594 SN74AHCT594
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
t
w
Pulse duration
RCLK or SRCLK high or low 5 5.5 5.5
ns
t
w
Pulse duration
RCLR
or SRCLR low 5.2 5.5 5.5
ns
SER before SRCLK↑ 3 3 3
SRCLK↑ before RCLK↑
‡
5 5 5
t
su
Setup time
SRCLR
low before RCLK↑ 5 5 5
ns
t
su
Setup time
SRCLR high (inactive) before SRCLK↑ 2.9 3.3 3.3
ns
RCLR high (inactive) before RCLK↑ 3.4 3.8 3.8
t
h
Hold time SER after SRCLK↑ 2 2 2 ns
‡
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
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