Datasheet

SN74AHCT125-Q1
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCLS508A − JUNE 2003 − REVISED FEBRUARY 2008
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D Qualified for Automotive Applications
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Inputs Are TTL-Voltage Compatible
description/ordering information
The SN74AHCT125 is a quadruple bus buffer gate
featuring independent line drivers with 3-state
outputs. Each output is disabled when the associated
output-enable (OE
) input is high. When OE is low, the
respective gate passes the data from the A input to
its Y output.
To ensure the high-impedance state during power up or power down, OE
should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
40°C to 125°C
SOIC − D Tape and reel SN74AHCT125QDRQ1 AHCT125Q
−40°C to 125°C
TSSOP − PW Tape and reel SN74AHCT125QPWRQ1 HB125Q
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OE A
OUTPUT
Y
L H H
L LL
H X Z
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1Y
2OE
2A
2Y
GND
V
CC
4OE
4A
4Y
3OE
3A
3Y
D OR PW PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (13 pages)