Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer, driver SOIC 14



   

  

SCLS549 − DECEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

D Extended Temperature Performance of

−40°C to 125°C

D Enhanced Diminishing Manufacturing

Sources (DMS) Support

D Enhanced Product-Change Notification

D Qualification Pedigree

†

Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

D ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

D Inputs Are TTL-Voltage Compatible

description/ordering information

The SN74AHCT125 is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each

output is disabled when the associated output-enable (OE

) input is high. When OE is low, the respective gate

passes the data from the A input to its Y output.

To ensure the high-impedance state during power up or power down, OE

should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

PACKAGE

‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−40°C to 125°C

SOIC − D Tape and reel SN74AHCT125QDREP AHCT125QEP

−40

C to 125

TSSOP − PW Tape and reel SN74AHCT125QPWREP HB125EP

‡

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

FUNCTION TABLE

(each buffer)

INPUTS

OUTPUT

OE A

OUTPUT

L H H

L LL

H X Z

1OE

2OE

GND

4OE

3OE

D OR PW PACKAGE

(TOP VIEW)

  !"# $ %&'# "$  (&)*%"# +"#',

+&%#$ %! # $('%%"#$ (' #-' #'!$  '."$ $#&!'#$

$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'

#'$#1  "** (""!'#'$,

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (12 pages)

PAGE 1
SCLS549 − DECEMBER 2003 D Controlled Baseline D D D D D ESD Protection Exceeds 2000 V Per − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −40°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Inputs Are TTL-Voltage Compatible D D OR PW PACKAGE (TOP VIEW) 1
PAGE 2
SCLS549 − DECEMBER 2003 logic diagram (positive logic) 1 1OE 1A 2 3 1Y 4 2OE 2A 5 6 2Y 10 3OE 3A 8 9 3Y 13 4OE 4A 12 11 4Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . .
PAGE 3
SCLS549 − DECEMBER 2003 recommended operating conditions (see Note 3) VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage VO IOH Output voltage IOL ∆t/∆v MIN MAX 4.5 5.5 High-level input voltage 2 UNIT V V 0.8 V 0 5.
PAGE 4
SCLS549 − DECEMBER 2003 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A Y CL = 15 pF tPZH tPZL OE Y CL = 15 pF tPHZ tPLZ OE Y CL = 15 pF tPLH tPHL A Y CL = 50 pF tPZH tPZL OE Y CL = 50 pF tPHZ tPLZ OE Y CL = 50 pF tsk(o) MIN TA = 25°C TYP MAX MIN MAX 3.8 5.5 1 6.
PAGE 5
SCLS549 − DECEMBER 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw 3V 1.5 V Input 1.5 V th tsu 3V 1.5 V Data Input 1.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74AHCT125QDREP Package Package Pins Type Drawing SOIC SN74AHCT125QPWREP TSSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AHCT125QDREP SOIC D 14 2500 333.2 345.9 28.6 SN74AHCT125QPWREP TSSOP PW 14 2000 367.0 367.0 35.
PAGE 9
PAGE 10
PAGE 11
PAGE 12
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.