Datasheet

SN54AHCT125, SN74AHCT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS264O − DECEMBER 1995 − REVISED JULY 2003
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OE A
OUTPUT
Y
L H H
L LL
H X Z
logic diagram (positive logic)
2A 2Y
2OE
1A 1Y
1OE
3A 3Y
3OE
4A 4Y
4OE
1
2
4
5
10
9
13
12
3
6
8
11
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.