SRCLK
SER
RCLK
SRCLR
OE
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
Q
H′
implies that the output is in 3-State mode.NOTE:
SN54AHC595, SN74AHC595
SCLS373J –MAY 1996–REVISED JULY 2013
www.ti.com
TIMING DIAGRAM
4 Submit Documentation Feedback Copyright © 1996–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHC595 SN74AHC595
