Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Standard Three-state, Inverted DIP 20

SN54ACT564, SN74ACT564

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCAS549B – NOVEMBER 1995 – REVISED NOVEMBER 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4.5-V to 5.5-V V

Operation

Inputs Accept Voltages to 5.5 V

Max t

of 8.5 ns at 5 V

Inputs Are TTL-Voltage Compatible

3-State Inverted Outputs Drive Bus Lines

Directly

Flow-Through Architecture to Optimize

PCB Layout

Full Parallel Access for Loading

description/ordering information

The ’ACT564 devices are octal D-type

edge-triggered flip-flops that feature 3-state

outputs designed specifically for driving highly

capacitive or relatively low-impedance loads.

They are particularly suitable for implementing

buffer registers, I/O ports, bidirectional bus

drivers, and working registers.

On the positive transition of the clock (CLK) input,

the Q

outputs are set to the complements of the

logic levels set up at the data (D) inputs.

A buffered output-enable (OE

) input places the

eight outputs in either a normal logic state (high or

low logic levels) or the high-impedance state. In

the high-impedance state, the outputs neither

load nor drive the bus lines significantly. The

high-impedance state and increased drive

provide the capability to drive bus lines without

interface or pullup components.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP – N Tube SN74ACT564N SN74ACT564N

SOIC DW

Tube SN74ACT564DW

ACT564

40°Cto85°C

SOIC

–

Tape and reel SN74ACT564DWR

ACT564

–

40°C

85°C

SOP – NS Tape and reel SN74ACT564NSR ACT564

SSOP – DB Tape and reel SN74ACT564DBR AD564

TSSOP – PW Tape and reel SN74ACT564PWR AD564

CDIP – J Tube SNJ54ACT564J SNJ54ACT564J

–55°C to 125°C

CFP – W Tube SNJ54ACT564W SNJ54ACT564W

LCCC – FK Tube SNJ54ACT564FK SNJ54ACT564FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

GND

CLK

SN54ACT564 ...J OR W PACKAGE

SN74ACT564 . . . DB, DW, N, NS, OR PW PACKAGE

(TOP VIEW)

3 2 1 20 19

910111213

GND

CLK

SN54ACT564 . . . FK PACKAGE

(TOP VIEW)

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (16 pages)

PAGE 1
SN54ACT564, SN74ACT564 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS549B – NOVEMBER 1995 – REVISED NOVEMBER 2002 D D SN54ACT564 . . . J OR W PACKAGE SN74ACT564 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) 4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 8.
PAGE 2
SN54ACT564, SN74ACT564 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS549B – NOVEMBER 1995 – REVISED NOVEMBER 2002 description/ordering information (continued) OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
PAGE 3
SN54ACT564, SN74ACT564 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS549B – NOVEMBER 1995 – REVISED NOVEMBER 2002 recommended operating conditions (see Note 3) SN54ACT564 MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 High-level output current IOL ∆t/∆v Low-level output current High-level input voltage SN74ACT564 MIN 2 2 V V 0.8 Input transition rise or fall rate UNIT 0.
PAGE 4
SN54ACT564, SN74ACT564 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS549B – NOVEMBER 1995 – REVISED NOVEMBER 2002 timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock tw Clock frequency tsu th Setup time, data before CLK↑ Hold time, data after CLK↑ tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) CLK Q OE Q OE Q MIN MAX SN74ACT564 MIN 65 MAX 75 UNIT MHz 3 5 3.
PAGE 5
SN54ACT564, SN74ACT564 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCAS549B – NOVEMBER 1995 – REVISED NOVEMBER 2002 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open 500 Ω CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC Open LOAD CIRCUIT 3V Timing Input 1.5 V 0V tw tsu 3V 1.5 V Input th 1.5 V 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS Output Control (low-level enabling) 3V 1.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com Orderable Device SN74ACT564PWRG4 28-Aug-2010 Status (1) ACTIVE Package Type Package Drawing TSSOP PW Pins 20 Package Qty 2000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) Contact TI Distributor or Sales Office (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ACT564DWR Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) DW 20 2000 330.0 24.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.8 13.0 2.7 12.0 24.0 Q1 SN74ACT564NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1 SN74ACT564PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ACT564DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74ACT564NSR SO NS 20 2000 367.0 367.0 45.0 SN74ACT564PWR TSSOP PW 20 2000 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 16
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