Datasheet

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SN74ACT1073

16-BIT BUS-TERMINATION ARRAY

WITH BUS-HOLD FUNCTION

SCAS193A − MARCH 1992 − REVISED NOVEMBER 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Designed to Ensure Defined Voltage Levels

on Floating Bus Lines in CMOS Systems

D 4.5-V to 5.5-V V

Operation

D Inputs Accept Voltages to 5.5 V

D Reduces Undershoot and Overshoot

Caused By Line Reflections

D Repetitive Peak Forward

Current ...I

FRM

= 100 mA

D Inputs Are TTL-Voltage Compatible

D Low Power Consumption (Like CMOS)

D Center-Pin V

and GND Configuration

Minimizes High-Speed Switching Noise

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

description/ordering information

This device is designed to terminate bus lines in CMOS systems. The integrated low-impedance diodes clamp

the voltage of undershoots and overshoots caused by line reflections and ensure signal integrity. The device

also contains a bus-hold function that consists of a CMOS-buffer stage with a high-resistance feedback path

between its output and its input. The SN74ACT1073 prevents bus lines from floating without using pullup or

pulldown resistors.

The high-impedance inputs of these internal buffers are connected to the input terminals of the device. The

feedback path on each internal buffer stage keeps a bus line tied to the bus holder at the last valid logic state

generated by an active driver before the bus switches to the high-impedance state.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC DW

Tube SN74ACT1073DW

ACT1073

−40°C to 85°C

SOIC − DW

Tape and reel SN74ACT1073DWR

ACT1073

40 C

85 C

SOP − NS Tape and reel SN74ACT1073NSR ACT1073

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

GND

D16

D15

D14

D13

D12

D11

D10

DW OR NS PACKAGE

(TOP VIEW)

Summary of content (12 pages)

PAGE 1
SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A − MARCH 1992 − REVISED NOVEMBER 2002 D Designed to Ensure Defined Voltage Levels D D D D D D D D DW OR NS PACKAGE (TOP VIEW) on Floating Bus Lines in CMOS Systems 4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Reduces Undershoot and Overshoot Caused By Line Reflections Repetitive Peak Forward Current . . .
PAGE 2
SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A − MARCH 1992 − REVISED NOVEMBER 2002 logic diagram, one of sixteen channels (positive logic) D1 VCC VCC 1 16 15 TG GND GND 6 5 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . .
PAGE 3
SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A − MARCH 1992 − REVISED NOVEMBER 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TA = 25°C TEST CONDITIONS MIN TYP† MAX MIN MAX UNIT IIL VCC = 4.5 to 5.5 V, VI = 0.8 V 0.15 0.3 0.9 0.1 1 mA IIH VCC = 4.5 to 5.5 V, VI = 2.5 V −0.2 −0.5 −1.4 −0.15 −1.5 mA VIKL IIN = −18 mA V VIKH IIN = 18 mA ICC‡ VCC = 5.
PAGE 4
SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A − MARCH 1992 − REVISED NOVEMBER 2002 TYPICAL CHARACTERISTICS FORWARD CURRENT vs INPUT VOLTAGE (LOWER CLAMPING DIODE) 60 5 55 0 50 −5 I F − Forward Current − mA I F − Forward Current − mA FORWARD CURRENT vs INPUT VOLTAGE (UPPER CLAMPING DIODE) 45 40 35 30 25 20 −10 −15 −20 −25 −30 −35 −40 15 −45 10 −50 5 −55 0 5.5 6 8 6.5 7 7.5 VI − Input Voltage − V 8.5 −60 −2 9 −1.75 −1.5 −1.25 −1 −0.75 −0.5 −0.
PAGE 5
SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193A − MARCH 1992 − REVISED NOVEMBER 2002 APPLICATION INFORMATION The SN74ACT1073 terminates the output of a driving device and holds the input of the driven device at the logic level of the driver output prior to establishment of the high-impedance state on that output (see Figure 5). Bus Typical Output Input CMOS Input Output D1 (external connection point) VCC 15 16 1 SN74ACT1073 5 6 GND Figure 5.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74ACT1073DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN74ACT1073NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ACT1073DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74ACT1073NSR SO NS 20 2000 367.0 367.0 45.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.