Datasheet

SN54ABTH18502A, SN54ABTH182502A, SN74ABTH18502A, SN74ABTH182502A
SCAN TEST DEVICES
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS164E – AUGUST 1993 – REVISED DECEMBER 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data
output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing
functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation
(PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
Improved scan efficiency is accomplished through the adoption of a one boundary-scan cell (BSC) per I/O pin
architecture. This architecture is implemented in such a way as to capture the most pertinent test data. A
PSA/COUNT instruction also is included to ease the testing of memories and other circuits where a binary count
addressing scheme is useful.
Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.
The B-port outputs of ’ABTH182502A, which are designed to source or sink up to 12 mA, include 25-Ω series
resistors to reduce overshoot and undershoot.
The SN54ABTH18502A and SN54ABTH182502A are characterized for operation over the full military
temperature range of –55°C to 125°C. The SN74ABTH18502A and SN74ABTH182502A are characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
†
(normal mode, each register)
INPUTS
OUTPUT
OEAB LEAB CLKAB A
B
L L L X B
0
‡
L L ↑ LL
L L ↑ HH
L HXLL
L HXHH
H X X X Z
†
A-to-B data flow is shown. B-to-A data flow is similar
but uses OEBA
, LEBA, and CLKBA.
‡
Output level before the indicated steady-state input
conditions were established